74LVC8T245-Q100;
74LVCH8T245-Q100
8-bit dual supply translating transceiver; 3-state
Rev. 1 — 21 March 2013
Product data sheet
1. General description
The 74LVC8T245-Q100; 74LVCH8T245-Q100 are 8-bit dual supply translating
transceivers with 3-state outputs that enable bidirectional level translation. They feature
two data input-output ports (pins An and Bn), a direction control input (DIR), an output
enable input (OE) and dual supply pins (V
CC(A)
and V
CC(B)
). Both V
CC(A)
and V
CC(B)
can be
supplied at any voltage between 1.2 V and 5.5 V. This flexibility makes the device suitable
for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and
5.0 V). Pins An, OE and DIR are referenced to V
CC(A)
and pins Bn are referenced to
V
CC(B)
. A HIGH on DIR allows transmission from An to Bn and a LOW on DIR allows
transmission from Bn to An. The output enable input (OE) can be used to disable the
outputs so the buses are effectively isolated.
The devices are fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either V
CC(A)
or V
CC(B)
are at
GND level, both A port and B port are in the high-impedance OFF-state.
Active bus hold circuitry in the 74LVCH8T245-Q100 holds unused or floating data inputs
at a valid logic level.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Wide supply voltage range:
V
CC(A)
: 1.2 V to 5.5 V
V
CC(B)
: 1.2 V to 5.5 V
High noise immunity
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
Nexperia
74LVC8T245-Q100; 74LVCH8T245-Q100
8-bit dual supply translating transceiver; 3-state
ESD protection:
MIL-STD-883, method 3015 Class 3A exceeds 4000 V
HBM JESD22-A114F Class 3A exceeds 4000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Maximum data rates:
420 Mbps (3.3 V to 5.0 V translation)
210 Mbps (translate to 3.3 V))
140 Mbps (translate to 2.5 V)
75 Mbps (translate to 1.8 V)
60 Mbps (translate to 1.5 V)
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78B Class II
24
mA output drive (V
CC
= 3.0 V)
Inputs accept voltages up to 5.5 V
Low power consumption: 30
A
maximum I
CC
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC8T245PW-Q100
74LVCH8T245PW-Q100
74LVC8T245BQ-Q100
74LVCH8T245BQ-Q100
40 C
to +125
C
40 C
to +125
C
Name
TSSOP24
Description
plastic thin shrink small outline package; 24
leads; body width 4.4 mm
Version
SOT355-1
SOT815-1
Type number
DHVQFN24 plastic dual in-line compatible thermal
enhanced very thin quad flat package; no
leads; 24 terminals; body 3.5
5.5
0.85 mm
74LVC_LVCH8T245_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 21 March 2013
2 of 28
Nexperia
74LVC8T245-Q100; 74LVCH8T245-Q100
8-bit dual supply translating transceiver; 3-state
4. Functional diagram
B1
21
V
CC(A)
V
CC(B)
B2
20
B3
19
B4
18
B5
17
B6
16
B7
15
B8
14
OE
22
DIR
2
3
A1
4
A2
5
A3
6
A4
7
A5
8
A6
9
A7
10
A8
001aai472
Fig 1.
Logic symbol
DIR
OE
A1
B1
V
CC(A)
V
CC(B)
to other seven channels
001aai473
Fig 2.
Logic diagram (one channel)
74LVC_LVCH8T245_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 21 March 2013
3 of 28
Nexperia
74LVC8T245-Q100; 74LVCH8T245-Q100
8-bit dual supply translating transceiver; 3-state
5. Pinning information
5.1 Pinning
/9&74
/9&+74
9
WHUPLQDO
LQGH[ DUHD
',5
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$
$
$
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$
$
*1'
*1'
*1'
9
9
2(
%
%
%
%
%
%
%
%
/9&74
/9&+74
9
',5
$
$
$
$
$
$
$
9
9
2(
%
%
%
%
%
%
%
%
*1'
DDD
$
*1'
$
*1'
*1'
DDD
7UDQVSDUHQW WRS YLHZ
(1) This is not a supply pin, the substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered the solder land should remain
floating or be connected to GND.
Fig 3.
Pin configuration SOT355-1 (TSSOP24)
Fig 4.
Pin configuration SOT815-1 (DHVQFN24)
5.2 Pin description
Table 2.
Symbol
V
CC(A)
DIR
A1 to A8
GND
[1]
GND
[1]
GND
[1]
B1 to B8
OE
V
CC(B)
V
CC(B)
[1]
Pin description
Pin
1
2
3, 4, 5, 6, 7, 8, 9, 10
11
12
13
22
23
24
Description
supply voltage A (An inputs/outputs, OE and DIR inputs are referenced to V
CC(A)
)
direction control
data input or output
ground (0 V)
ground (0 V)
ground (0 V)
output enable input (active LOW)
supply voltage B (Bn inputs/outputs are referenced to V
CC(B)
)
supply voltage B (Bn inputs/outputs are referenced to V
CC(B)
)
21, 20, 19, 18, 17, 16, 15, 14 data input or output
All GND pins must be connected to ground (0 V).
74LVC_LVCH8T245_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 21 March 2013
4 of 28
Nexperia
74LVC8T245-Q100; 74LVCH8T245-Q100
8-bit dual supply translating transceiver; 3-state
6. Functional description
Table 3.
Function table
[1]
Input
OE
[2]
L
L
H
X
DIR
[2]
L
H
X
X
Input/output
[3]
An
[2]
An = Bn
input
Z
Z
Bn
[2]
input
Bn = An
Z
Z
Supply voltage
V
CC(A)
, V
CC(B)
1.2 V to 5.5 V
1.2 V to 5.5 V
1.2 V to 5.5 V
GND
[3]
[1]
[2]
[3]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
The An inputs/outputs, DIR and OE input circuit is referenced to V
CC(A)
; The Bn inputs/outputs circuit is referenced to V
CC(B)
.
If at least one of V
CC(A)
or V
CC(B)
is at GND level, the device goes into suspend mode.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC(A)
V
CC(B)
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
[4]
Parameter
supply voltage A
supply voltage B
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
0.5
0.5
Max
+6.5
+6.5
-
+6.5
-
V
CCO
+ 0.5
+6.5
50
100
-
+150
500
Unit
V
V
mA
V
mA
V
V
mA
mA
mA
C
mW
V
I
< 0 V
[1]
50
0.5
50
[1][2][3]
[1]
[2]
V
O
< 0 V
Active mode
Suspend or 3-state mode
V
O
= 0 V to V
CCO
I
CC(A)
or I
CC(B)
; per V
CC
pin
per GND pin
T
amb
=
40 C
to +125
C
[4]
0.5
0.5
-
-
100
65
-
The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.
V
CCO
is the supply voltage associated with the output port.
V
CCO
+ 0.5 V should not exceed 6.5 V.
For TSSOP24 package: P
tot
derates linearly at 5.5 mW/K above 60
C.
For DHVQFN24 package: P
tot
derates linearly at 4.5 mW/K above 60
C.
74LVC_LVCH8T245_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 21 March 2013
5 of 28
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