MB9B420TA Series
32-bit Arm
®
Cortex
®
-M3
FM3 Microcontroller
The MB9B420TA Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption
mode and competitive cost.
These series are based on the Arm
®
Cortex
®
-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions
such as various timers, ADCs, DACs and Communication Interfaces (CAN, UART, CSIO, I
2
C, LIN).
The products which are described in this data sheet are placed into TYPE12 product categories in "FM3 Family Peripheral Manual".
Features
32-bit Arm
®
Cortex
®
-M3 Core
Processor version: r2p1
Up to 60 MHz Frequency Operation
Integrated Nested Vectored Interrupt Controller (NVIC):
1 NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
management
CAN Interface
Compatible with CAN Specification 2.0A/B
Maximum transfer rate: 1 Mbps
Built-in 32 message buffer
Multi-function Serial Interface (Max 16 channels)
16 channels with 16 steps×9-bit FIFO
Operation mode is selectable from the followings for each
channel.
UART
CSIO
LIN
I
2
C
24-bit System timer (Sys Tick): System timer for OS task
On-chip Memories
[Flash memory]
Dual operation Flash memory
Main
area:
• Up to 1.5 Mbytes(1008 Kbytes(ROM0) + 512 Kbytes
(ROM1) of Upper bank and 16 Kbytes (ROM0) of Lower
bank.)
Work area
• 64 Kbytes(ROM1) of Lower bank
[UART]
Full duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control: Automatically control the
transmission/reception by CTS/RTS (only ch.4)
framing errors, and overrun errors)
Read cycle: 0 wait-cycle
Security function for code protection
[SRAM]
This Series on-chip SRAM is composed of two independent
SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus
and D-code bus of Cortex-M3 core. SRAM1 is connected to
System bus.
Various error detection functions available (parity errors,
[CSIO]
Full duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
[LIN]
LIN protocol Rev.2.1 supported
Full duplex double buffer
Master/Slave mode supported
LIN break field generation (can be changed to 13 to 16-bit
length)
length)
SRAM0: Up to 96 Kbytes
SRAM1: Up to 96 Kbytes
External Bus Interface
Supports SRAM, NOR NAND Flash memory device
Up to 8 chip selects
8-/16-bit Data width
Up to 25-bit Address bit
Maximum area size: Up to 256 Mbytes
Supports Address/Data multiplex
Supports external RDY function
LIN break delimiter generation (can be changed to 1 to 4-bit
Various error detection functions available (parity errors,
framing errors, and overrun errors)
Cypress Semiconductor Corporation
Document Number: 002-05663 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 12, 2018
MB9B420TA Series
[I
2
C]
Standard - mode (Max 100 kbps) / Fast - mode (Max 400
kbps) supported
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when
they are not used for external bus or peripherals. Moreover,
the port relocate function is built in. It can set which I/O port
the peripheral function can be allocated to.
DMA Controller (8 channels)
The DMA Controller has an independent bus from the CPU, so
CPU and DMA Controller can process simultaneously.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up to 154 high-speed general-purpose I/O Ports@176pin
Package
8 independently configured and operated channels
Transfer can be started by software or request from the built-
in peripherals
Transfer address area: 32-bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Some ports are 5V tolerant.
See "4. List of Pin Functions" and "5. I/O Circuit Type" to
confirm the corresponding pins.
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
A/D Converter (Max 24 channels)
[12-bit A/D Converter]
Successive Approximation type
Built-in 2units
Conversion time: 1.0μs @ 2.7V to 5.5V
Priority conversion available (priority at 2levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
D/A Converter (Max 2 channels)
R-2R type
10-bit resolution
Base Timer (Max 16 channels)
Operation mode is selectable from the followings for each
channel.
conversion: 16 steps, for Priority conversion: 4 steps)
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
Free-running
Periodic (=Reload)
One-shot
Quadrature Position/Revolution Counter (QPRC)
(Max 2channels)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use as the up/down counter.
The detection edge of the three external event input pins
AIN, BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
HDMI-CEC/Remote Control Reception (Up to
2 channels)
HDMI-CEC transmission
block automatic transmission by judging Signal
free
Generating status interrupt by detecting Arbitration lost
Generating START, EOM, ACK automatically to output
CEC transmission by setting 1 byte data
Generating transmission status interrupt when transmitting
1 block (1 byte data and EOM/ACK)
Header
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
HDMI-CEC reception
ACK reply function available
Line error detection function available
Automatic
Remote control reception
4
bytes reception buffer
Repeat code detection function available
Document Number: 002-05663 Rev. *E
Page 2 of 134
MB9B420TA Series
Multi-function Timer
The Multi-function timer is composed of the following blocks.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator calculates the CRC which has a heavy
software processing load, and achieves a reduction of the
integrity check processing load for reception data and storage.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
16-bit free-run timer × 3 ch./unit
Input capture × 4 ch./unit
Output compare × 6 ch./unit
A/D activation compare × 2 ch./unit
Waveform generator × 3 ch./unit
16-bit PPG timer × 3 ch./unit
The following function can be used to achieve the motor
control.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
[Clocks]
Selectable from five clock sources (2 external oscillators, 2
built-in CR oscillators, and Main PLL).
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
Real-time clock (RTC)
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
Main Clock:
Sub Clock:
4 MHz to 48 MHz
32.768 kHz
Built-in high-speed CR Clock: 4 MHz
Built-in low-speed CR Clock: 100 kHz
Main PLL Clock
[Resets]
Reset requests from INITX pin
Power-on reset
Software reset
Watchdog timers reset
Low-voltage detection reset
Clock Super Visor reset
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to
supervise abnormality of the external clocks.
The interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute.) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
Watch Counter
The Watch counter is used for wake up from sleep and timer
mode.
Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
If external clock failure (clock stop) is detected, reset is
asserted.
If external frequency anomaly is detected, interrupt or reset
is asserted.
External Interrupt Controller Unit
Up to 32 external interrupt input pins @ 176pin Package
Include one non-maskable interrupt (NMI) input pin
Watchdog Timer (2 channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
The "Hardware" watchdog timer is clocked by the built-in low-
speed CR oscillator. Therefore, the "Hardware" watchdog is
active in any low-power consumption modes except RTC,
STOP, Deep standby RTC, Deep standby STOP modes.
Low-Voltage Detector (LVD)
This Series includes 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage that has been
set, Low-Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Document Number: 002-05663 Rev. *E
Page 3 of 134
MB9B420TA Series
Low-Power Consumption Mode
Six low-power consumption modes supported.
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocell (ETM)
Unique ID
Unique value of the device (41-bit) is set.
SLEEP
TIMER
RTC
STOP
Deep standby RTC (selectable between keeping the value of
RAM and not)
Power Supply
Wide range voltage: VCC = 2.7 V to 5.5 V
Deep standby STOP (selectable between keeping the value
of RAM and not)
Document Number: 002-05663 Rev. *E
Page 4 of 134
MB9B420TA Series
Contents
1. Product Lineup .................................................................................................................................................................. 7
2. Packages ........................................................................................................................................................................... 8
3. Pin Assignment ................................................................................................................................................................. 9
4. List of Pin Functions....................................................................................................................................................... 12
5. I/O Circuit Type................................................................................................................................................................ 53
6. Handling Precautions ..................................................................................................................................................... 59
6.1
Precautions for Product Design ................................................................................................................................... 59
6.2
Precautions for Package Mounting .............................................................................................................................. 60
6.3
Precautions for Use Environment ................................................................................................................................ 61
7. Handling Devices ............................................................................................................................................................ 62
8. Block Diagram ................................................................................................................................................................. 64
9. Memory Size .................................................................................................................................................................... 64
10. Memory Map .................................................................................................................................................................... 65
11. Pin Status in Each CPU State ........................................................................................................................................ 68
12. Electrical Characteristics ............................................................................................................................................... 76
12.1 Absolute Maximum Ratings ......................................................................................................................................... 76
12.2 Recommended Operating Conditions.......................................................................................................................... 78
12.3 DC Characteristics....................................................................................................................................................... 79
12.3.1 Current Rating .............................................................................................................................................................. 79
12.3.2 Pin Characteristics ....................................................................................................................................................... 82
12.4 AC Characteristics ....................................................................................................................................................... 83
12.4.1 Main Clock Input Characteristics .................................................................................................................................. 83
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 84
12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 85
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL) .................................................. 86
12.4.5 Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock of main PLL).............. 86
12.4.6 Reset Input Characteristics .......................................................................................................................................... 87
12.4.7 Power-on Reset Timing................................................................................................................................................ 87
12.4.8 External Bus Timing ..................................................................................................................................................... 88
12.4.9 Base Timer Input Timing .............................................................................................................................................. 98
12.4.10 CSIO/UART Timing .................................................................................................................................................. 99
12.4.11 External Input Timing .............................................................................................................................................. 107
12.4.12 Quadrature Position/Revolution Counter timing ...................................................................................................... 108
12.4.13 I
2
C Timing ............................................................................................................................................................... 110
12.4.14 ETM Timing ............................................................................................................................................................ 111
12.4.15 JTAG Timing ........................................................................................................................................................... 112
12.5 12-bit A/D Converter .................................................................................................................................................. 113
12.6 10-bit D/A Converter .................................................................................................................................................. 116
12.7 Low-Voltage Detection Characteristics ...................................................................................................................... 117
12.7.1 Low-Voltage Detection Reset ..................................................................................................................................... 117
12.7.2 Interrupt of Low-Voltage Detection ............................................................................................................................. 118
12.8 Flash Memory Write/Erase Characteristics ............................................................................................................... 119
12.8.1 Write / Erase time....................................................................................................................................................... 119
12.8.2 Write cycles and data hold time ................................................................................................................................. 119
12.9 Return Time from Low-Power Consumption Mode .................................................................................................... 120
12.9.1 Return Factor: Interrupt/WKUP .................................................................................................................................. 120
Document Number: 002-05663 Rev. *E
Page 5 of 134
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