CY62167DV18 MoBL
®
16-Mbit (1M x 16) Static RAM
Features
• Very high speed: 55 ns
• Wide voltage range: 1.65V–1.95V
• Ultra low active power
— Typical active current: 1.5 mA @ f = 1 MHz
•
•
•
•
•
— Typical active current: 15 mA @ f = f
max
Ultra low standby power
Easy memory expansion with CE
1
, CE
2
, and OE features
Automatic power down when deselected
CMOS for optimum speed and power
Available in Pb-free 48-ball VFBGA package
consumption by more than 99% when deselected (CE
1
HIGH
or CE
2
LOW or both BHE and BLE are HIGH). The input and
output pins (IO
0
through IO
15
) are placed in a high impedance
state when:
• Deselected (CE
1
HIGH or CE
2
LOW)
• Outputs are disabled (OE HIGH)
• Both Byte High Enable (BHE) and Byte Low Enable (BLE)
are disabled (BHE, BLE HIGH)
• Write operation is active (CE
1
LOW, CE
2
HIGH and WE
LOW)
To write to the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW. If BLE is LOW, then
data from IO pins (IO
0
through IO
7
) is written into the location
specified on the address pins (A
0
through A
19
). If BHE is LOW
then data from IO pins (IO
8
through IO
15
) is written into the
location specified on the address pins (A
0
through A
19
).
To read from the device, take Chip Enables (CE
1
LOW and
CE
2
HIGH) and OE LOW while forcing the WE HIGH. If BLE
is LOW, then data from the memory location specified by the
address pins appear on IO
0
to IO
7
. If BHE is LOW, then data
from memory appears on IO
8
to IO
15
. See the
“Truth Table” on
page 9
for a complete description of read and write modes.
Functional Description
[1]
The CY62167DV18 is a high performance CMOS static RAM
organized as 1M words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. Placing the device into standby mode reduces power
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
1M × 16
RAM Array
SENSE AMPS
IO
0
–IO
7
IO
8
–IO
15
COLUMN DECODER
BYTE
BHE
WE
OE
CE
2
CE
1
BLE
CE
2
CE
1
Power Down
Circuit
BHE
BLE
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at
http://www.cypress.com.
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
Cypress Semiconductor Corporation
Document Number : 38-05326 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 19,2010
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CY62167DV18 MoBL
®
DC Input Voltage
[4, 5]
........................–0.2V to V
CCmax
+ 0.2V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current..................................................... > 200 mA
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of
the device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential . –0.2V to V
CCmax
+ 0.2V
DC Voltage Applied to Outputs
in High-Z State
[4, 5]
........................... –0.2V to V
CCmax
+ 0.2V
Operating Range
Range
Industrial
Ambient
Temperature
–40°C to +85°C
V
CC
[6]
1.65V to 1.95V
DC Electrical Characteristics
(Over the Operating Range)
55 ns
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
V
CC
Operating Supply Current
Automatic CE Power down
Current
−
CMOS Inputs
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
f = f
MAX
= 1/t
RC
f = 1 MHz
V
CC
= 1.95V, I
OUT
= 0 mA,
CMOS level
Test Conditions
I
OH
=
−0.1
mA
I
OL
= 0.1 mA
1.4
–0.2
–1
–1
15
1.5
2.5
Min
1.4
0.2
V
CC
+ 0.2
0.4
+1
+1
30
5
20
μA
Typ
[2]
Max
Unit
V
V
V
V
μA
μA
mA
CE
1
> V
CC
−
0.2V, CE
2
< 0.2V,
V
IN
> V
CC
−
0.2V, V
IN
< 0.2V,
f = f
MAX
(Address and Data Only),
f = 0 (OE, WE, BHE and BLE)
CE
1
> V
CC
−
0.2V, CE
2
< 0.2V,
V
IN
> V
CC
−
0.2V or V
IN
< 0.2V,
f = 0, V
CC
=1.95V
I
SB2
Automatic CE Power down
Current
−
CMOS Inputs
2.5
20
μA
Capacitance
[7]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz, V
CC
= V
CC(typ)
Max
6
8
Unit
pF
pF
Notes
4. V
IL(min)
= –2.0V for pulse durations less than 20 ns.
5. V
IH(max)
= V
CC
+ 0.75V for pulse durations less than 20 ns.
6. Full device AC operation requires linear V
CC
ramp from 0 to V
CC(min)
and V
CC
must be stable at V
CC(min)
for 500
μs.
7. Tested initially and after any design or process changes that may affect these parameters.
Document Number : 38-05326 Rev. *D
Page 3 of 11
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CY62167DV18 MoBL
®
Thermal Resistance
[7]
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
VFBGA
55
16
Unit
°C/W
°C/W
AC Test Loads and Waveforms
V
CC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R1
V
CC
R2
GND
Rise Time = 1 V/ns
Equivalent to:
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
THEVENIN EQUIVALENT
R
TH
OUTPUT
V
1.8V
13500
10800
6000
0.80
Unit
Ω
Ω
Ω
V
Parameters
R1
R2
R
TH
V
TH
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
t
CDR[7]
t
R[8]
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
V
CC
= 1.0V, CE > V – 0.2V, CE < 0.2V,
1
CC
2
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V
0
t
RC
Conditions
Min
1.0
Typ
[2]
Max
1.95
10
Unit
V
μA
ns
ns
Data Retention Waveform
[9]
V
CC
CE
1
or
BHE
,
BLE
V
CC
, min
t
CDR
DATA RETENTION MODE
V
DR
> 1.0V
V
CC
, min
t
R
or
CE
2
Notes
8. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100
μs
or stable at V
CC(min)
> 100
μs.
9. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number : 38-05326 Rev. *D
Page 4 of 11
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