PN5180A0xx/C3
Rev. 3.2 — 20 December 2017
436532
High-performance multi-protocol full NFC frontend,
supporting all NFC Forum modes
Product data sheet
COMPANY PUBLIC
1
Introduction
This document describes the functionality and electrical specification of the high-power
NFC IC PN5180A0HN/C3, PN5180A0ET/C3, firmware versions equal or higher than
FW3.A.
The package description of the PN5180A0ET/C3 is described in an addendum to this
document.
Additional documents supporting a design-in of the PN5180 are available from NXP, this
additional design-in information is not part of this document.
NXP Semiconductors
High-performance multi-protocol full NFC frontend, supporting all NFC Forum modes
PN5180A0xx/C3
2
General description
PN5180, the best full NFC frontend on the market.
As a highly integrated high performance full NFC Forum-compliant frontend IC for
contactless communication at 13.56 MHz, this frontend IC utilizes an outstanding
modulation and demodulation concept completely integrated for different kinds of
contactless communication methods and protocols.
The PN5180 ensures maximum interoperability for next generation of NFC enabled
mobile phones. The PN5180 is optimized for point of sales terminal applications and
implements a high-power NFC frontend functionality which allows to achieve EMV
compliance on RF level without additional external active components.
The PN5180 frontend IC supports the following RF operating modes:
•
•
•
•
•
•
•
•
•
•
•
•
•
Reader/Writer mode supporting ISO/IEC 14443-A up to 848 kBit/s, MIFARE
Reader/Writer mode supporting ISO/IEC 14443-B up to 848 kBit/s
Reader/Writer mode supporting JIS X 6319-4 (comparable with FeliCa scheme)
Supports reading of all NFC tag types (type 1, type 2, type 3, type 4A and type 4B)
Reader/Writer mode supporting ISO/IEC 15693
Reader/Writer mode supporting ISO/IEC 18000-3 Mode 3
ISO/IEC 18092 (NFC-IP1)
ISO/IEC 21481 (NFC-IP-2)
ISO/IEC 14443-type A Card emulation up to 848 kBit/s
SPI interface with data rates up to 7 Mbit/s with MOSI, MISO, NSS and SCK signals
Interrupt request line to inform host controller on events
EEPROM configurable pull-up resistor on SPI MISO line
Busy line to indicate to host availability of data for reading
One host interface based on SPI is implemented:
The PN5180 supports highly innovative and unique features which do not require any
host controller interaction. These unique features include Dynamic Power Control
(DPC), Adaptive Waveform Control (AWC), Adaptive Receiver Control (ARC), and fully
automatic EMD error handling. The independency of real-time host controller interactions
makes this product the best choice for systems which operate a preemptive multi-tasking
OS like Linux or Android.
As new power-saving feature the PN5180 allows using a general-purpose output to
control an external LDO or DC/DC during Low-Power Card Detection. One general-
purpose output is used to wake-up an LDO or DC/DC from power-saving mode before
the RF field for an LPCD polling cycle is switched on.
The PN5180 supports an external silicon system-power-on switch by using the energy
of the RF field generated by an NFC phone to switch on the system, like it is generated
during the NFC polling loop. This unique and new Zero-Power-Wake-up feature allows
designing systems with a power consumption close to zero during standby.
PN5180
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.2 — 20 December 2017
436532
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NXP Semiconductors
High-performance multi-protocol full NFC frontend, supporting all NFC Forum modes
PN5180A0xx/C3
3
Features and benefits
•
Transmitter current up to 250 mA
•
Dynamic Power Control (DPC) for optimized RF performance, even under detuned
antenna conditions
•
Adaptive Waveform Control (AWC) automatically adjusts the transmitter modulation for
RF compliancy
•
Adaptive Receiver Control (ARC) automatically adjusts the receiver parameters for
always reliable communication
•
Includes NXP ISO/IEC14443-A and Innovatron ISO/IEC14443-B intellectual property
licensing rights
•
Full compliancy with all standards relevant to NFC, contactless operation and EMVCo
•
Active load modulation supports smaller antenna in Card Emulation Mode
•
Automatic EMD handling performed without host interaction relaxes the timing
requirements on the Host Controller
•
Low-power card detection (LPCD) minimizes current consumption during polling
•
Automatic support of system LDO or system DC/DC power-down mode during LPCD
•
Zero-Power-Wake-up
•
Small, industry-standard packages
•
NFC Cockpit: PC-based support tool for fast configuration of register settings
•
Development kit with 32-bit NXP LPC1769 MCU and antenna
•
NFC Reader Library with source code ready for EMVCo L1 and NFC Forum
compliance
PN5180
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.2 — 20 December 2017
436532
3 / 158
NXP Semiconductors
High-performance multi-protocol full NFC frontend, supporting all NFC Forum modes
PN5180A0xx/C3
4
Applications
•
•
•
•
Payment
Physical-access
eGov
Industrial
PN5180
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.2 — 20 December 2017
436532
4 / 158
NXP Semiconductors
High-performance multi-protocol full NFC frontend, supporting all NFC Forum modes
PN5180A0xx/C3
5
Quick reference data
Parameter
supply voltage on pin VBAT
supply voltage on pin PVDD
supply voltage on pin TVDD
power-down current
Conditions
-
1.8 V supply
3.3 V supply
-
VDD(TVDD) = VDD(PVDD)
=VDD(VDD) 3.0 V; hard
power-down; pin RESET_N
set LOW, T
amb
= 25 °C
T
amb
= 25 °C
-
limiting value
in still air with exposed
pins soldered on a 4 layer
JEDEC PCB
no supply voltage applied
Min
2.7
1.65
2.7
2.7
-
Typ
3.3
1.8
3.3
5.0
10
Max
5.5
1.95
3.6
5.5
-
Unit
V
V
V
V
μA
Table 1. Quick reference data
Symbol
V
DD(VBAT)
V
DD(PVDD)
V
DD(TVDD)
I
pd
I
stb
I
DD(TVDD)
T
amb
standby current
supply current on pin TVDD
ambient temperature
-
-
-
-30
15
180
-
+25
-
250
300
+85
μA
mA
mA
°C
T
stg
storage temperature
-55
+25
+150
°C
PN5180
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.2 — 20 December 2017
436532
5 / 158
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