EZ-PD™ CCG4
USB Type-C Port Controller
General Description
EZ-PD™ CCG4 is a dual USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD CCG4 provides
a complete dual USB Type-C and USB-Power Delivery port control solution for notebooks, power adapters and docking stations. It
can also be used in dual role and downstream facing port applications. EZ-PD CCG4 uses Cypress’s proprietary M0S8 technology
with a 32-bit, 48-MHz ARM
®
Cortex
®
-M0 processor with 128 KB flash and integrates two complete Type-C Transceivers including the
Type-C termination resistors R
P
and R
D
.
Applications
Notebooks
■
Power adapters
■
Docking stations
■
Low-Power Operation
■
■
■
2.7-V to 5.5-V operation
Independent supply voltage pin for GPIO that allows 1.71-V to
5.5-V signaling on the I/Os
Reset: 1.0 µA, Deep Sleep: 2.5 µA, Sleep: 2.5 mA
± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based
on IEC61000-4-2 level 4C
Features
32-bit MCU Subsystem
48-MHz ARM Cortex-M0 CPU
■
128-KB Flash
■
8-KB SRAM
■
System-Level ESD on CC Pins
■
Hot Swappable I/Os
■
Port 1 I
2
C pins and CC1, CC2 pins are hot-swappable
4.0 mm
4.0 mm, 0.5 mm, 24-pin QFN
6.0 mm
6.0 mm, 0.6 mm, 40-pin QFN
Supports industrial temperature range (–40 °C to +85 °C)
Integrated Digital Blocks
Up to four integrated timers and counters to meet response
times required by the USB-PD protocol
■
Four run-time serial communication blocks (SCBs) with
reconfigurable I
2
C, SPI, or UART functionality
■
Packages
■
■
■
Clocks and Oscillators
■
Integrated oscillator eliminating the need for external clock
Type-C and USB-PD Support
Integrated USB Power Delivery 3.0 support
■
Two integrated USB-PD BMC transceivers
[1]
[2]
■
Integrated UFP (R
D
) and current sources for DFP (R
P
) on
both Type-C ports
■
Integrated dead battery termination for DRP (Power
Source/Sink) applications
■
Supports two USB Type-C ports
■
Integrated VCONN FETs to power EMCA cables
■
Integrated fast role swap and extended data messaging
■
Notes
1. UFP refers to Power Sink.
2. DFP refers to Power Source.
Cypress Semiconductor Corporation
Document Number: 001-98440 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 10, 2017
EZ-PD™ CCG4
Logic Block Diagram
CCG4: Single-Chip Type-C Controller
MCU Subsystem
Integrated Digital Blocks
4 x TCPWM
1
Programmable I/O Matrix
CORTEX-M0
I/O Subsystem
CC_PORT1
5
CC_PORT2
5
2x V
CONN
FETs
(PORT1)
2x V
CONN
FETs
(PORT2)
GPIOs
6
4 x SCB
2
(I
2
C, SPI, UART)
Advanced High-Performance Bus (AHB)
48 MHz
Profiles and
Configurations
Flash
(128KB)
2 x Baseband MAC
2 x Baseband PHY
SRAM
(8KB)
Integrated R
d3
and R
p4
4 x 8-bit SAR ADC
Serial Wire Debug
1. Timer, counter, pulse width modulation block
2. Serial communication block configurable as UART, SPI, or I
2
C
3. Termination resistor denoting a UFP
4. Current Sources to indicate a DFP
5. Configuration Channel
6. General purpose input/output
Document Number: 001-98440 Rev. *I
Page 2 of 32
EZ-PD™ CCG4
Available Firmware and Software Tools
EZ-PD Configuration Utility
The EZ-PD Configuration Utility is a GUI-based Microsoft Windows application developed by Cypress to guide a CCGx user through
the process of configuring and programming the chip. The utility allows users to:
1. Select and configure the parameters they want to modify
2. Program the resulting configuration onto the target CCGx device.
The utility works with the Cypress supplied CCG1, CCG2, CCG3, and CCG4 kits, which host the CCGx controllers along with a USB
interface. This version of the EZ-PD Configuration Utility supports configuration and firmware update operations on CCGx controllers
implementing EMCA and Display Dongle applications. Support for other applications, such as Power Adapters and Notebook port
controllers, will be provided in later versions of the utility.
You can download the EZ-PD Configuration Utility and its associated documentation at the following link:
http://www.cypress.com/documentation/software-and-drivers/ez-pd-configuration-utility
Document Number: 001-98440 Rev. *I
Page 3 of 32
EZ-PD™ CCG4
Contents
Functional Overview ........................................................ 6
CPU and Memory Subsystem ..................................... 6
USB-PD Subsystem (SS) ............................................ 6
System Resources ...................................................... 7
Peripherals .................................................................. 7
GPIO ........................................................................... 8
Pinouts .............................................................................. 9
Power ............................................................................... 15
Application Diagrams ..................................................... 16
Electrical Specifications ................................................ 18
Absolute Maximum Ratings ...................................... 18
Device-Level Specifications ...................................... 18
Digital Peripherals ..................................................... 21
Memory ..................................................................... 22
System Resources .................................................... 22
Ordering Information ...................................................... 25
Ordering Code Definitions ......................................... 25
Packaging ........................................................................ 26
Acronyms ........................................................................ 28
Document Conventions ................................................. 29
Units of Measure ....................................................... 29
References and Links To Applications Collaterals .... 30
Document History Page ................................................. 31
Sales, Solutions, and Legal Information ...................... 32
Worldwide Sales and Design Support ....................... 32
Products .................................................................... 32
PSoC® Solutions ...................................................... 32
Cypress Developer Community ................................. 32
Technical Support ..................................................... 32
Document Number: 001-98440 Rev. *I
Page 4 of 32
EZ-PD™ CCG4
Figure 1. EZ-PD CCG4 Block Diagram
CPU Subsystem
CCG4
32-bit
SWD/TC
SPCIF
Cortex
M0
48 MHz
FAST MUL
NVIC, IRQMX
FLASH
128 KB
Read Accelerator
SRAM
8 KB
SRAM Controller
ROM
8 KB
ROM Controller
AHB-Lite
System Resources
Lite
Power
Sleep Control
WIC
POR
REF
PWRSYS
Clock
Clock Control
WDT
IMO
ILO
System Interconnect (Single Layer AHB)
Peripherals
PCLK
Peripheral Interconnect (MMIO)
2 x USB-PD 3.0
IOSS GPIO
(5 x ports)
4 x TCPWM
4 x SCB
Reset
Reset Control
XRES
Test
DFT Logic
DFT Analog
Power Modes
Active/Sleep
Deep Sleep
High Speed I/O Matrix
27 x GPIOs, 2 OVTs
Pads, ESD
I/O Subsystem
Document Number: 001-98440 Rev. *I
2 X VCONN FET
2 x SAR ADC
CC BB PHY
Page 5 of 32
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