W134
Direct Rambus™ Clock Generator
Features
• Differential clock source for Direct Rambus™ memory
subsystem for up to 800-MHz data transfer rate
• Provide synchronization flexibility: the Rambus
®
Channel can optionally be synchronous to an external
system or processor clock
• Power-managed output allows Rambus Channel clock
to be turned off to minimize power consumption for
mobile applications
• Works with Cypress CY2210, W133, W158, W159, W161,
and W167 to support Intel
®
architecture platforms
• Low-power CMOS design packaged in a 24-pin QSOP
(150-mil SSOP) package
Description
The Cypress W134M/W134S provides the differential clock
signals for a Direct Rambus memory subsystem. It includes
signals to synchronize the Direct Rambus Channel clock to an
external system clock but can also be used in systems that do
not require synchronization of the Rambus clock.
Block Diagram
REFCLK
MULT0:1
Pin Configuration
VDDIR
REFCLK
VDD
GND
GND
PCLKM
SYNCLKN
GND
VDD
VDDIPD
STOPB
PWRDNB
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
S0
S1
VDD
GND
CLK
NC
CLKB
GND
VDD
MULT0
MULT1
GND
PLL
PCLKM
SYNCLKN
Phase
Alignment
Output
Logic
CLK
CLKB
S0:1
Test
Logic
STOPB
........................ Document #: 38-07426 Rev. *C Page 1 of 11
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W134
Pin Definitions
Pin Name
REFCLK
PCLKM
No.
2
6
Type
I
I
Description
Reference Clock Input.
Reference clock input, normally supplied by a system frequency
synthesizer (Cypress W133).
Phase Detector Input.
The phase difference between this signal and SYNCLKN is used
to synchronize the Rambus Channel Clock with the system clock. Both PCLKM and
SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio
Logic is not used, this pin would be connected to Ground.
Phase Detector Input.
The phase difference between this signal and PCLKM is used to
synchronize the Rambus Channel Clock with the system clock. Both PCLKM and
SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio
Logic is not used, this pin would be connected to Ground.
Clock Output Enable.
When this input is driven to active LOW, it disables the differential
Rambus Channel clocks.
Active LOW Power-down.
When this input is driven to active LOW, it disables the differ-
ential Rambus Channel clocks and places the W134M/W134S in power-down mode.
PLL Multiplier Select.
These inputs select the PLL prescaler and feedback dividers to
determine the multiply ratio for the PLL for the input REFCLK.
MULT0
0
0
1
1
MULT1
0
1
1
0
W134M
PLL/REFCLK
4.5
6
8
5.333
W134S
PLL/REFCLK
4
6
8
5.333
SYNCLKN
7
I
STOPB
PWRDNB
MULT 0:1
11
12
15, 14
I
I
I
CLK, CLKB
S0, S1
20, 18
24, 23
O
I
Complementary Output Clock.
Differential Rambus Channel clock outputs.
Mode Control Input.
These inputs control the operating mode of the W134M/W134S.
S0
0
0
1
1
S1
0
1
0
1
MODE
Normal
Output Enable Test
Bypass
Test
NC
VDDIR
VDDIPD
VDD
GND
19
1
10
3, 9, 16, 22
4, 5, 8, 13, 17,
21
–
No Connect
RefV
Reference for REFCLK.
Voltage reference for input reference clock.
RefV
Reference for Phase Detector.
Voltage reference for phase detector inputs and StopB.
P
G
Power Connection.
Power supply for core logic and output buffers. Connected to 3.3V
supply.
Ground Connection.
Connect all ground pins to the common system ground plane.
W133
W158
W159
W161
W167
CY2210
W134M/W134S
Refclk
PLL
Phase
Align
D
Busclk
Pclk/M
RMC
RAC
Synclk/N
M
Pclk
N
Synclk
4
DLL
Gear
Ratio
Logic
Figure 1. DDLL System Architecture
........................ Document #: 38-07426 Rev. *C Page 2 of 11
W134
Key Specifications
Supply Voltage:...................................... V
DD
= 3.3V±0.165V
Operating Temperature: ................................... 0°C to +70°C
Input Threshold:...................................................1.5V typical
Maximum Input Voltage: ........................................ V
DD
+0.5V
Maximum Input Frequency: ..................................... 100 MHz
Output Duty Cycle:................................... 40/60% worst case
Output Type: ........................... Rambus signaling level (RSL)
(Rambus Channel). At the mid-point of the channel, the RAC
senses Busclk using its own DLL for clock alignment, followed
by a fixed divide-by-4 that generates Synclk.
Pclk is the clock used in the memory controller (RMC) in the
core logic, and Synclk is the clock used at the core logic
interface of the RAC. The DDLL together with the Gear Ratio
Logic enables users to exchange data directly from the Pclk
domain to the Synclk domain without incurring additional
latency for synchronization. In general, Pclk and Synclk can
be of different frequencies, so the Gear Ratio Logic must
select the appropriate M and N dividers such that the
frequencies of Pclk/M and Synclk/N are equal. In one inter-
esting example, Pclk = 133 MHz, Synclk = 100 MHz, and
M = 4 while N = 3, giving Pclk/M = Synclk/N = 33 MHz. This
example of the clock waveforms with the Gear Ratio Logic is
shown in
Figure 2.
The output clocks from the Gear Ratio Logic, Pclk/M, and
Synclk/N, are output from the core logic and routed to the
DRCG Phase Detector inputs. The routing of Pclk/M and
Synclk/N must be matched in the core logic as well as on the
board.
After comparing the phase of Pclk/M vs. Synclk/N, the DRCG
Phase Detector drives a phase aligner that adjusts the phase
of the DRCG output clock, Busclk. Since everything else in the
distributed loop is fixed delay, adjusting Busclk adjusts the
phase of Synclk and thus the phase of Synclk/N. In this
manner the distributed loop adjusts the phase of Synclk/N to
match that of Pclk/M, nulling the phase error at the input of the
DRCG Phase Detector. When the clocks are aligned, data can
be exchanged directly from the Pclk domain to the Synclk
domain.
Table 1
shows the combinations of Pclk and Busclk
frequencies of greatest interest, organized by Gear Ratio.
DDLL System Architecture and Gear Ratio
Logic
Figure 1
shows the Distributed Delay Lock Loop (DDLL)
system architecture, including the main system clock source,
the Direct Rambus clock generator (DRCG), and the core logic
that contains the Rambus Access Cell (RAC), the Rambus
Memory Controller (RMC), and the Gear Ratio Logic. (This
diagram abstractly represents the differential clocks as a
single Busclk wire.)
The purpose of the DDLL is to frequency-lock and phase-align
the core logic and Rambus clocks (Pclk and Synclk) at the
RMC/RAC boundary in order to allow data transfers without
incurring additional latency. In the DDLL architecture, a PLL is
used to generate the desired Busclk frequency, while a
distributed loop forms a DLL to align the phase of Pclk and
Synclk at the RMC/RAC boundary.
The main clock source drives the system clock (Pclk) to the
core logic, and also drives the reference clock (Refclk) to the
DRCG. For typical Intel architecture platforms, Refclk will be
half the CPU front side bus frequency. A PLL inside the DRCG
multiplies Refclk to generate the desired frequency for Busclk,
and Busclk is driven through a terminated transmission line
Table 1. Supported Pclk and Busclk Frequencies, by Gear Ratio
Gear Ratio and Busclk
Pclk
67 MHz
100 MHz
133 MHz
150 MHz
200 MHz
400 MHz
267 MHz
356 MHz
400 MHz
300 MHz
400 MHz
2.0
1.5
1.33
1.0
267 MHz
400 MHz
Pclk
Synclk
Pclk/M =
Synclk/N
Figure 2. Gear Ratio Timing Diagram
........................ Document #: 38-07426 Rev. *C Page 3 of 11
W134
S0/S1 StopB
W133
W158
W159
W161
W167
CY2210
W134M/W134S
Refclk
PLL
Phase
Align
D
Busclk
Pclk/M
RMC
RAC
Synclk/N
M
Pclk
N
Synclk
4
DLL
Gear
Ratio
Logic
Figure 3. DDLL Including Details of DRCG
Figure 3
shows more details of the DDLL system architecture,
including the DRCG output enable and bypass modes.
Phase Detector Signals
The DRCG Phase Detector receives two inputs from the core
logic, PclkM (Pclk/M) and SynclkN (Synclk/N). The M and N
dividers in the core logic are chosen so that the frequencies of
PclkM and SynclkN are identical. The Phase Detector detects
the phase difference between the two input clocks, and drives
the DRCG Phase Aligner to null the input phase error through
the distributed loop. When the loop is locked, the input phase
error between PclkM and SynclkN is within the specification
t
ERR,PD
given in the Device Characteristics table after the lock
time given in the State Transition Section.
The Phase Detector aligns the rising edge of PclkM to the
rising edge of SynclkN. The duty cycle of the phase detector
input clocks will be within the specification DC
IN,PD
given in the
Operating Conditions table. Because the duty cycles of the two
phase detector input clocks will not necessarily be identical,
the falling edges of PclkM and SynclkN may not be aligned
when the rising edges are aligned.
The voltage levels of the PclkM and SynclkN signals are deter-
mined by the controller. The pin VDDIPD is used as the voltage
reference for the phase detector inputs and should be
connected to the output voltage supply of the controller. In
some applications, the DRCG PLL output clock will be used
directly, by bypassing the Phase Aligner. If PclkM and SynclkN
are not used, those inputs must be grounded.
Selection Logic
Table 2
shows the logic for selecting the PLL prescaler and
feedback dividers to determine the multiply ratio for the PLL
from the input Refclk. Divider A sets the feedback and divider
B sets the prescaler, so the PLL output clock frequency is set
by: PLLclk = Refclk*A/B.
Table 2. PLL Divider Selection
W134M
Mult0
0
0
1
1
Mult1
0
1
1
0
A
9
6
8
16
B
2
1
1
3
A
4
6
8
16
W134S
B
1
1
1
3
Table 3
shows the logic for enabling the clock outputs, using
the StopB input signal. When StopB is HIGH, the DRCG is in
its normal mode, and Clk and ClkB are complementary outputs
following the Phase Aligner output (PAclk). When StopB is
LOW, the DRCG is in the Clk Stop mode, the output clock
drivers are disabled (set to Hi-Z), and the Clk and ClkB settle
to the DC voltage V
X,STOP
as given in the Device Character-
istics table. The level of V
X,STOP
is set by an external resistor
network.
Table 3. Clock Stop Mode Selection
Mode
Normal
Clk Stop
StopB
1
0
Clk
PAclk
V
X,STOP
ClkB
PAclkB
V
X,STOP
Table 4
shows the logic for selecting the Bypass and Test
modes. The select bits, S0 and S1, control the selection of
these modes. The Bypass mode brings out the full-speed PLL
output clock, bypassing the Phase Aligner. The Test mode
brings the Refclk input all the way to the output, bypassing
both the PLL and the Phase Aligner. In the Output Test mode
(OE), both the Clk and ClkB outputs are put into a
high-impedance state (Hi-Z). This can be used for component
testing and for board-level testing.
........................ Document #: 38-07426 Rev. *C Page 4 of 11
W134
Table 4. Bypass and Test Mode Selection
Mode
Normal
Output Test (OE)
Bypass
Test
S0
0
0
1
1
S1
0
1
0
1
Bypclk
(int.)
Gnd
–
PLLclk
Refclk
Clk
PAclk
Hi-Z
PLLclk
Refclk
ClkB
PAclkB
Hi-Z
PLLclkB
RefclkB
and S1 must be stable before power is applied to the device,
and can only be changed in Power-down mode (PwrDnB = 0).
The reference inputs, V
DDR
and V
DDPD
, may remain on or may
be grounded during the Power-down mode.
Table 6. Examples of Frequencies, Dividers, and Gear Ratios
Pclk Refclk Busclk Synclk A B M N Ratio F@PD
67
100
100
133
133
33
50
50
67
67
267
300
400
267
400
67
75
100
67
100
8 1 2 2
6 1 8 6
8 1 4 4
4 1 4 2
6 1 8 6
1.0
1.33
1.0
2.0
1.33
33
12.5
25
33
16.7
Table 5
shows the logic for selecting the Power-down mode,
using the PwrDnB input signal. PwrDnB is active LOW
(enabled when 0). When PwrDnB is disabled, the DRCG is in
its normal mode. When PwrDnB is enabled, the DRCG is put
into a powered-off state, and the Clk and ClkB outputs are
three-stated.
Table 5. Power-down Mode Selection
Mode
Normal
Power-down
PwrDnB
1
0
Clk
PAclk
GND
ClkB
PAclkB
GND
The control signals Mult0 and Mult1 can be used in two ways.
If they are changed during Power-down mode, then the
Power-down transition timings determine the settling time of
the DRCG. However, the Mult0 and Mult1 control signals can
also be changed during Normal mode. When the Mult control
signals are “hot-swapped” in this manner, the Mult transition
timings determine the settling time of the DRCG.
In Normal mode, the clock source is on, and the output is
enabled.
Table 7
lists the control signals for each state.
Table 7. Control Signals for Clock Source States
State
Power-down
Clock Stop
Normal
PwrDnB
0
1
1
StopB
X
0
1
Clock
Source
OFF
ON
ON
Output
Buffer
Ground
Disabled
Enabled
Table of Frequencies and Gear Ratios
Table 6
shows several supported Pclk and Busclk
frequencies, the corresponding A and B dividers required in
the DRCG PLL, and the corresponding M and N dividers in the
gear ratio logic. The column Ratio gives the Gear Ratio as
defined Pclk/Synclk (same as M and N). The column F@PD
gives the divided down frequency (in MHz) at the Phase
Detector, where F@PD = Pclk/M = Synclk/N.
State Transitions
The clock source has three fundamental operating states.
Figure 4
shows the state diagram with each transition labelled
A through H. Note that the clock source output may NOT be
glitch-free during state transitions.
Upon powering up the device, the device can enter any state,
depending on the settings of the control signals, PwrDnB and
StopB.
In Power-down mode, the clock source is powered down with
the control signal, PwrDnB, equal to 0. The control signals S0
Figure 5
shows the timing diagrams for the various transitions
between states, and
Table 8
specifies the latencies of each
state transition. Note that these transition latencies assume
the following.
Refclk input has settled and meets specification shown in the
Operating Conditions table.
The Mult0, Mult1, S0 and S1 control signals are stable.
VDD Turn-On
M
L
Test
K
VDD Turn-On
N
B
A
Power-Down
VDD Turn-On
J
G
Normal
F
E
D
C
Clk Stop
VDD Turn-On
H
Figure 4. Clock Source State Diagram
........................ Document #: 38-07426 Rev. *C Page 5 of 11
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