Obsolete Product – Not Recommended for New Designs
PKS603-607
PeakSwitch
Family
Product Highlights
®
Enhanced, Energy-Efficient, Off-Line Switcher
IC With Super Peak Power Performance
EcoSmart
– Extremely Energy-Efficient
• Standby output power ≥0.6 W for 1 W input (high line)
• Sleep mode power ≥2.4 W at 3 W input (high line)
• No-load consumption <200 mW at 265 VAC input
• Surpasses California Energy Commission (CEC),
ENERGY STAR, and EU requirements
PeakSwitch
Features Reduce System Cost
• Delivers peak power of up to three times maximum
continuous output power
• 277 kHz operation during peak power significantly
reduces transformer size
• Programmable smart AC line sensing provides latching
shutdown during short circuit, overload and open loop
faults, and prevents glitches during power down or
brownout
• Two external components reset latch on AC removal
• Adaptive switching cycle on-time extension increases low
line peak output power, minimizing bulk capacitor size
• Adaptive current limit reduces output overload power
• Frequency jittering reduces EMI filter cost
• Tight I
2
f tolerances and negligible temperature variation
of key parameters ease design and lower cost
• Accurate hysteretic thermal shutdown with automatic
recovery provides complete system level overload
protection and eliminates need for manual reset
Better System Cost/Performance over RCC & Discrete
• Simple ON/OFF control – no loop compensation needed
• Very low component count – higher reliability and single
side printed circuit board
• High bandwidth provides fast turn on with no overshoot
and excellent transient load response
• Peak current limit operation rejects line frequency ripple
• Built-in current limit and hysteretic thermal protection
Applications
• Inkjet printer
• Data storage, audio amplifier, DC motor drives
®
AC
IN
+
DC
OUT
Optional Smart
AC Sense
PeakSwitch
D
EN/UV
BP
S
PI-3995-051006
Figure 1. Typical Peak Power Application.
PRODUCT
3
PKS603 P
PKS604 P
PKS604 Y/F
PKS605 P
PKS605 Y/F
PKS606 P
PKS606 Y/F
PKS607 Y/F
Table 1.
OUTPUT POWER TABLE
230 VAC 15%
85-265 VAC
Adapter Adapter Adapter Adapter
Cont.
1
Peak
2
Cont.
1
Peak
2
13 W
23 W
35 W
31 W
46 W
35 W
68 W
75 W
32 W
56 W
56 W
60 W
79 W
66 W
117 W
126 W
9W
16 W
23 W
21 W
30 W
25 W
45 W
50 W
25 W
44 W
44 W
44 W
58 W
46 W
86 W
93 W
Notes:
1. Typical continuous power in a non-ventilated enclosed adapter
measured at +50 °C ambient.
2. Typical peak power for a period of 100 ms and a duty cycle of
10% in a non-ventilated enclosed adapter measured at +50 °C
(see Key Applications section for details).
3. See Part Ordering Information.
Description
PeakSwitch is designed to address applications with high peak-
to-continuous power ratio demands. The very high switching
frequency during peak power loads and excellent load transient
response reduce system cost as well as component count and size.
PeakSwitch incorporates a 700 V power MOSFET, oscillator,
high voltage switched current source for startup, current limit,
and thermal shutdown onto a monolithic device. In addition,
these devices incorporate auto-restart, line under-voltage sense
and frequency jittering. An innovative design minimizes audio
frequency components in the simple ON/OFF control scheme
to practically eliminate audible noise with standard varnished
transformer construction.
February 2007
PKS603-607
BYPASS
(BP)
DRAIN
(D)
REGULATOR
5.8 V
25 A
LINE UNDER-VOLTAGE
LATCH OFF/
AUTO-
RESTART
COUNTER
ON TIME EXT
RESET
FAULT
PRESENT
CURRENT
LIMIT STATE
MACHINE/
ADAPTIVE
CURRENT
LIMIT
+
240 A
BYPASS PIN
UNDER-VOLTAGE
5.8 V
4.8 V
-
V
I
LIMIT
6.3 V
ENABLE
CURRENT LIMIT
COMPARATOR
-
+
1.0 V + V
T
JITTER
CLOCK
DCMAX
OSCILLATOR
THERMAL
SHUTDOWN
ENABLE/
UNDER-
VOLTAGE
(EN/UV)
1.0 V
S
Q
R
Q
LEADING
EDGE
BLANKING
SOURCE
(S)
GROUND (GND)
(Y & F Package
Only)
PI-3940-040606
Figure 2. Functional Block Diagram.
Pin Functional Description
Y Package (TO-220-7C)
Tab Internally
Connected to
SOURCE Pin
7D
5 NC
4S
3 EN/UV
2 GND
1 BP
DRAIN (D) Pin:
The power MOSFET drain connection provides internal
operating current for both startup and steady-state operation.
BYPASS (BP) Pin:
A 0.33 µF external bypass capacitor for the internally generated
5.8 V supply is connected to this pin. In typical applications,
this pin must be externally supplied via a bias winding.
ENABLE/UNDER-VOLTAGE (EN/UV) Pin:
This pin has dual functions: enable input and line under-voltage
sense. During normal operation, switching of the power MOSFET
is controlled by this pin. MOSFET switching is disabled when a
current greater than 240 µA is drawn from this pin. This pin may
also sense line under-voltage conditions through either an external
resistor connected to the DC line voltage or an AC sense circuit.
SOURCE (S) Pin:
This is the MOSFET source connection for high voltage return
and control circuit common.
P Package (DIP-8C)
BP
EN/UV
1
2
8
7
6
D
4
5
S
S
S
S
F Package (TO-262-7C)
7D
5 NC
4S
3 EN/UV
2 GND
1 BP
PI-3941-031506
Figure 3. Pin Configuration.
GROUND (GND) Pin (Y or F Package Only):
This is the signal ground for the bypass capacitor and optocoupler.
2
Rev. I 02/07
PKS603-607
PeakSwitch
Functional Description
PeakSwitch integrates a 700 V power MOSFET switch with a
power supply controller on the same die. Unlike conventional
pulse width modulation (PWM) controllers, PeakSwitch uses a
simple ON/OFF control to regulate the output voltage.
The controller consists of an oscillator, enable
circuit (sense and logic), current-limit state machine,
5.8 V regulator, BYPASS pin under-voltage circuit, over-
temperature protection, current limit circuit, and leading
edge blanking.
PeakSwitch
incorporates additional circuitry
for adaptive current limit, line under-voltage sense,
programmable smart line sense, auto-restart, adaptive
switching cycle on-time extension, and frequency jitter.
Figure 2 is a functional block diagram of the device’s most
important features.
Oscillator
The typical oscillator frequency is internally set to an average
of 277 kHz. Two signals are generated from the oscillator: the
maximum duty cycle (DC
MAX
) signal and the clock signal that
indicates the beginning of each cycle.
The oscillator incorporates circuitry that introduces a small
amount of frequency jitter, typically 16 kHz peak-to-peak, to
minimize EMI emission. The modulation rate of the frequency
jitter is set to 1.1 kHz to optimize EMI reduction for both
average and quasi-peak emissions. The frequency jitter should
be measured with the oscilloscope triggered at the falling edge
of the DRAIN waveform. The waveform in Figure 4 illustrates
the frequency jitter.
Enable Input and Current-Limit State Machine
The enable input circuit at the EN/UV pin consists of a low
impedance source follower output set at 1.0 V. The current
through the source follower is limited to 240 µA. When the
PI-3942-022806
current out of this pin exceeds 240 µA, a low logic level
(disable) is generated at the output of the enable circuit. This
enable circuit output is sampled at the beginning of each
cycle on the rising edge of the clock signal. If high, the power
MOSFET is turned on for that cycle (enabled). If low, the power
MOSFET remains off (disabled). Since the sampling is done
only at the beginning of each cycle, subsequent changes in the
EN/UV pin voltage or current during the remainder of the
cycle are ignored.
The current-limit state machine reduces the current limit by
discrete amounts at light loads when
PeakSwitch
is likely to
switch in the audible frequency range. The lower current limit
raises the effective switching frequency above the audio range
and reduces the transformer flux density, including the associated
audible noise. The state machine monitors the sequence of
EN/UV pin voltage levels to determine the load condition and
adjusts the current limit level accordingly in discrete amounts.
Under most operating conditions (except when close to no-load),
the low impedance of the source follower keeps the voltage on
the EN/UV pin from going much below 1.0 V in the disabled
state. This improves the response time of the optocoupler that
is usually connected to this pin.
5.8 V Regulator and 6.3 V Shunt Voltage Clamp
The 5.8 V regulator charges the bypass capacitor connected to
the BYPASS pin to 5.8 V by drawing a current from the voltage
on the DRAIN pin whenever the MOSFET is off. The BYPASS
pin is the internal supply voltage node. When the MOSFET
is on, the PeakSwitch operates from the energy stored in the
bypass capacitor. The voltage on the DRAIN pin powers the
bypass during start-up.
There is a 6.3 V shunt regulator clamping the BYPASS pin at
6.3 V when current is provided through an external resistor
from the bias winding in normal operation. Powering the
PeakSwitch device in this way minimizes no-load consumption
to about 150 mW at 265 VAC. Note that a bias winding must be
used to power the device. See Key Application Considerations
section for details.
BYPASS Pin Under-Voltage
The BYPASS pin under-voltage circuitry disables the power
MOSFET when the BYPASS pin voltage drops below 4.8 V.
Once the BYPASS pin voltage drops below 4.8 V, it must rise
back to 5.8 V to enable (turn on) the power MOSFET.
600
500
V
DRAIN
400
300
200
100
0
285 kHz
269 kHz
0
2.5
Time (µs)
5
Figure 4. Frequency Jitter.
Over Temperature Protection
The thermal shutdown circuitry senses the die temperature.
The threshold is typically set at 142 °C with 75 °C hysteresis.
When the die temperature rises above this threshold, the
power MOSFET is disabled and remains disabled until the die
temperature falls by 75 °C, at which point it is re-enabled. A large
hysteresis of 75 °C (typical) is provided to prevent overheating
3
Rev. I 02/07
PKS603-607
of the PC board during a continuous fault condition.
Current Limit
The current limit circuit senses the current in the power MOSFET.
When this current exceeds the internal threshold (I
LIMIT
), the
power MOSFET is turned off for the remainder of that cycle. The
current limit state machine reduces the current limit threshold
by discrete amounts under medium and light loads.
The leading edge blanking circuit inhibits the current limit
comparator for a short time (t
LEB
) after the power MOSFET is
turned on. This leading edge blanking time has been set so that
current spikes caused by capacitance and secondary-side rectifier
reverse recovery time will not cause premature termination of
the MOSFET conduction portion of the switching cycle.
During startup and fault conditions, the controller prevents
excessive drain currents by reducing the switching frequency.
Adaptive Current Limit
When switching in the full current limit state, a skipped cycle
followed by a cycle that terminates at the full current limit
implies that the line voltage is at high line. Under this condition,
adaptive current limit reduces the full current limit level by
approximately 10% in order to reduce output overload power.
The next skipped cycle disables the adaptive current limit
condition and restores the full current limit level.
Line Under-Voltage Sense Circuit
The line under-voltage circuit prevents startup below the
programmed input voltage by connecting an external resistor
from either the DC line or from an AC sense circuit (see
Figure 1) to the EN/UV pin. The complete function is described
in the flow chart shown in Figure 5. During power up or when
the switching of the power MOSFET is disabled in auto-restart,
the current flowing into the EN/UV pin must exceed 25 µA to
initiate switching of the power MOSFET. During power up,
once the threshold is exceeded, the Bypass pin must charge from
4.8 V to 5.8 V before MOSFET switching is initiated.
The line under-voltage circuit also detects when there is no
external resistor connected to the EN/UV pin (less than ~1 µA
into pin). In this case, the line under-voltage function is disabled
and the device operates with a normal auto-restart function.
Programmable Smart AC Line Sense
When an external AC sense circuit is used (see Figure 1), the line
under-voltage sense circuit can be used to determine the reason
for a loss of feedback signal at the EN/UV pin. In the event of
a fault condition such as output overload, output short circuit,
or an open loop condition, the power MOSFET switching is
disabled after the EN/UV pin is not pulled low for 30 ms. If the
AC line is present (I
EN
> 25 µA) at the time switching is disabled,
the line under-voltage sense circuit prevents a
restart attempt until the AC input voltage is removed
No
No
1. Startup
2. UV Resistor
Present?
No
9. Start Switching
Yes
3. AC Input
Present?
(I
EN
>25 A)
10. No Feedback
>30 ms?
No
Yes
Yes
11. Stop Switching
(for 5 s)
4. Start Switching
5. No Feedback
>30 ms?
Yes
6. Stop Switching
Yes
7. AC Input
Present?
(I
EN
>25 A)
Note: Normal operation
(no fault present) is denoted
by looping with a “No” response
at decision box 5 or 10.
No
8. Reset A/R Latch
PI-4014-062305
Figure 5. PeakSwitch Line Sense Function Flow Chart.
4
Rev. I 02/07
PKS603-607
V
DRAIN
PI-3943-031506
PeakSwitch
Operation
PeakSwitch devices operate in the current-limit mode. When
enabled, the oscillator turns the power MOSFET on at the
beginning of each cycle. The MOSFET is turned off when the
current ramps up to the current limit or when the DC
MAX
limit
is reached. Since the highest current limit level and frequency
of a
PeakSwitch
design are constant, the power delivered
to the load is proportional to the primary inductance of the
transformer and peak primary current squared. Hence, designing
300
200
100
0
10
V
DC-OUTPUT
5
0
V
EN
0
5
10
CLOCK
D
Time (s)
Figure 6. PeakSwitch Auto-Restart Operation.
(I
EN
<25 µA). Then the internal auto-restart latch is reset and
the power MOSFET switching will resume once the AC input
voltage is applied again (I
EN
>25 µA). This effectively provides
a latching shutdown function with AC reset during such a fault
condition.
When a brownout or line sag occurs, output regulation may
be lost and the EN/UV pin will receive no feedback (it is
pulled low). After 30 ms of no feedback, MOSFET switching
is disabled. Since the AC line is abnormally low (I
EN
<25 µA)
MOSFET switching remains disabled until normal line voltage
is restored. The power MOSFET switching will resume once
the AC input returns to normal (I
EN
>25 µA). This effectively
disables the latching shutdown function during such a condition.
Auto-Restart (UV resistor not present)
In the event of a fault condition such as output overload,
output short circuit or an open loop condition,
PeakSwitch
enters into auto-restart operation. An internal counter
clocked by the oscillator is reset every time the EN/UV pin
is pulled low. When the EN/UV pin receives no feedback
for 30 ms, the power MOSFET switching is disabled for
5 seconds (150 ms for the first auto-restart event). The
auto-restart alternately enables and disables the switching
of the power MOSFET until the fault condition is removed.
Figure 6 illustrates auto-restart circuit operation in the presence
of an output short circuit.
Adaptive Switching Cycle On-time Extension
Adaptive switching cycle on-time extension keeps the MOSFET
on until current limit is reached, instead of terminating after
the DC
MAX
signal goes low. This on-time extension is adaptive
because it only occurs after the ENABLE pin has been high
for approximately 750 µs, a condition that would arise if the
peak output power was required in low line conditions. On-time
extension is disabled during the startup of the power supply.
MAX
I DRAIN
V DRAIN
PI-2749-050301
Figure 7. PeakSwitch Operation at Near Maximum Loading.
V
EN
CLOCK
D
MAX
I DRAIN
V DRAIN
PI-2667-090700
Figure 8. PeakSwitch Operation at Moderately Heavy Loading.
5
Rev. I 02/07
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