NCP1937
Combination Power Factor
Correction and Quasi-
Resonant Flyback
Controllers for Adapters
This combination IC integrates power factor correction (PFC) and
quasi−resonant flyback functionality necessary to implement a
compact and highly efficient Switched Mode Power Supply for an
adapter application.
The PFC stage exhibits near−unity power factor while operating in a
Critical Conduction Mode (CrM) with a maximum frequency clamp.
The circuit incorporates all the features necessary for building a robust
and compact PFC stage while minimizing the number of external
components.
The quasi−resonant current−mode flyback stage features a
proprietary valley−lockout circuitry, ensuring stable valley switching.
This system works down to the 4
th
valley and toggles to a frequency
foldback mode with a minimum frequency clamp beyond the 4
th
valley to eliminate audible noise. Skip mode operation allows
excellent efficiency in light load conditions while consuming very low
standby power consumption.
Common General Features
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MARKING DIAGRAM
HV/X2
BO/X2
PControl
SOIC−20
PONOFF
Narrow Body
QCT
CASE 751BS
Fault
PSTimer
QFB
1
NCP1937xxG
AWLYWW
20
PFBHV
PFBLV
GND
PCS/PZCD
PDRV
QDRV
QCS
VCC
QZCD
NCP1937 = Specific Device Code
xx
= A1, A2, A3, B1, B2, B3, C1, C4 or C61
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
•
Wide V
CC
Range from 9 V to 30 V with Built−in Overvoltage
•
•
•
•
Protection
ORDERING INFORMATION
See detailed ordering and shipping information on page 5 of
High−Voltage Startup Circuit and Active Input Filter Capacitor
this data sheet.
Discharge Circuitry for Reduced Standby Power
Integrated High−Voltage Brown−Out Detector
Integrated High−Voltage Switch Disconnects PFC Feedback Resistor
Divider to Reduce Standby Power
Fault Input for Severe Fault Conditions, NTC
•
Feed−Forward for Improved Operation across Line and
Compatible (Latch and Auto−Recovery Options)
Load
0.5 A / 0.8 A Source / Sink Gate Drivers
•
Adjustable PFC Disable Threshold Based on Output
Power
Internal Temperature Shutdown
Consumption to 70
mA
Enabling Very Low Input Power
Applications
QR Flyback Controller Features
•
•
•
Power Savings Mode Reduces Supply Current
•
Valley Switching Operation with Valley−Lockout for
•
•
•
•
•
•
Noise−Free Operation
Frequency Foldback with Minimum Frequency Clamp
for Highest Performance in Standby Mode
Minimum Frequency Clamp Eliminates Audible Noise
Timer−Based Overload Protection (Latched or
Auto−Recovery options)
Adjustable Overpower Protection
Winding and Output Diode Short−Circuit Protection
4 ms Soft−Start Timer
PFC Controller Features
•
Critical Conduction Mode with Constant On Time
•
•
•
•
Control (Voltage Mode) and Maximum Frequency
Clamp
Accurate Overvoltage Protection
Bi−Level Line−Dependent Output Voltage
Fast Line / Load Transient Compensation
Boost Diode Short−Circuit Protection
©
Semiconductor Components Industries, LLC, 2015
1
June, 2015 − Rev. 4
Publication Order Number:
NCP1937/D
L
PDRV
N L
VCC
(Aux)
PCS/PZCD
PCS/PZCD
PDRV
QCS
VCC
QCS
HV/X2
VZCD
NCP1937
Figure 1. Typical Application Circuit
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N
2
PFBHV
PFBLV
BO/X2
GND
PControl PCS/PZCD
PONOFF
PDRV
QCT
QDRV
Fault
QCS
PSTimer
VCC
QZCD
QFB
NCP1937
VZCD
VPSTimer
PSM Control
NCP1937
PFBHV
20
Enable
PFC
+
PUVP
V
PFB(HYS)
PFC
OVP
Detection
I
PControl(boost)
V
−
PFB(disable)
Latch
Auto−recovery
V
CC(reset)
Line Removal
Brownout
POVP
Low/High Line
VCC_OK
In PSM
QR_EN
PFCDRV
BO/X2
Low/High Line
High Voltage
Brownout
Startups,
Line Removal
Detection, and
VCC_OK
Logic
QR_EN
Central
In PSM
Logic
Reset
I
start
V
CCOVP
VCC
VCC_OK
Management
V
CC(reset)
V
DD
Line Removal
I
CC(discharge)
Soft−start
V
QILIM1
V
QFB
QZCD
Soft−Start
I
PONOFF
+
V
−
POFF
3
HV/X2
1
PFBLV
18
K
POVP(xL)
D
POVP(xL)
VCC
12
C
CC
K
LOW
+
K
LOW(HYS)
I
EA
Low/High Line
ON Time
Ramp
Level
Shift
V
PREF(xL)
PControl
5
−
In Regulation
V
PCONTROL(MAX)
Low
Clamp
PUVP
Disable PFC
PSKIP
+
DV
−
PSKIP
In Regulation
PONOFF
6
Disable PFC
t
Pisable
V
PONHYS
PDRV
15
PFCDRV
POVP
PUVP
PSKIP
PILIM1
PILIM2
R
Q
Dominant
Reset Latch
Q
S
PFCDRV
R
Q
Dominant
Reset
S Latch Q
t
Q(toutx)
Valley
ZCD
Detect
PILIM2
PFCDRV
PFCDRV
t
PFC(off)
Timer
Frequency
Clamp
ZCD
Detect
PZCD
t
delay(QSKIP)
Minimum
Frequency
Oscillator
V
QZCD(th)
CT
V
QFB
VCO Setpoint
QRDRV
I
QCT
VCO
QRDRV
7
QSkip
PCS/PZCD
16
+
V
−
PZCD
PZCD
LEB1
+
−
I
PCS/PZCD
t
P(tout)
I
QFB
PILIM1
QSkip
t
onQR(MAX)
nPILIM2
QRDRV
TSD
QOVLD
nQILIM2
nPILIM2
OVP
OTP
V
CCOVP
S
S
S
S
S
S
S
R
R
R
Temperature
TSD
nQILIM2
+
V
QZCD
Latch
Fault
Logic
QILIM1
Auto−recovery
QOVLD
t
QOVLD
V
QZCD
QILIM2
Counter
+
I
QCS
QCS
13
17
R
QFB
Valley
QSkip
VCO
Valley
Select
Logic
In_PSM
V
QFB
/K
QFB
GND
QFB
10
V
PILIM1
PILIM2
Counter
LEB2
I
OTP
Fault
8
+
− V
PILIM2
OVP
V
Fault(OVP)
OTP
LEB1
V
Fault(OTP_in)
I
PSTimer1/2
PSTIMER
9
Line Removal
Brownout
V
CC(reset)
In_PSM
PSM
Detection
V
QILIM1
LEB2
−
+
V
QILIM2
In PSM
VCC_OK
Initial Discharge
Figure 2. Functional Block Diagram
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3
−
+
+
−
QRDRV
QDRV
14
Soft−start
V
QZCD
QZCD
11
V
QZCD(hys)
QCT
−
+
+
−
NCP1937
Table 1. PIN FUNCTION DESCRIPTION
Pin Out
1
2
3
4
5
6
PControl
PONOFF
BO/X2
Name
HV/X2
Function
High voltage startup circuit input. It is also used to discharge the input filter capacitors.
Removed for creepage distance.
Performs brown−out detection for the whole IC and it is also used to discharge the input filter capacitors
and detect the line voltage range.
Removed for creepage distance.
Output of the PFC transconductance error amplifier. A compensation network is connected between this
pin and ground to set the loop bandwidth.
A resistor between this pin and ground sets the PFC turn off threshold. The voltage on this pin is com-
pared to an internal voltage signal proportional to the output power. The PFC disable threshold is de-
termined by the resistor on this pin and the internal pull–up current source, I
PONOFF
.
An external capacitor sets the frequency in VCO mode for the QR flyback controller.
The controller enters fault mode if the voltage of this pin is pulled above or below the fault thresholds. A
precise pull up current source allows direct interface with an NTC thermistor. Fault detection triggers a
latch or auto−recovery depending on device option.
Power savings mode (PSM) control and timer adjust. Compatible with an optocoupler for secondary con-
trol of PSM. The device enters PSM if the voltage on this pin exceeds the PSM threshold, V
PS_in
. A capa-
citor between this pin and GND sets the delay time before the controller enters power savings mode.
Once the controller enters power savings mode the IC is disabled and the current consumption is re-
duced to a maximum of 70
mA.
The input filter capacitor discharge function is available while in power
savings mode. The controller is enabled once V
PSTimer
drops below V
PS_out
.
Feedback input for the QR Flyback controller. Allows direct connection to an optocoupler.
Input to the demagnetization detection comparator for the QR Flyback controller. Also used to set the
overpower compensation.
Supply input.
Input to the cycle−by−cycle current limit comparator for the QR Flyback section.
QR flyback controller switch driver.
PFC controller switch driver.
Input to the cycle−by−cycle current limit comparator for the PFC section. Also used to perform the de-
magnetization detection for the PFC controller.
Ground reference.
Low voltage PFC feedback input. An external resistor divider is used to sense the PFC bulk voltage. The
divider low side resistor connects to this pin. This voltage is compared to an internal reference. The refer-
ence voltage is 2.5 V at low line and 4 V at high line. An internal high−voltage switch disconnects the low
side resistor from the high side resistor chain when the PFC is disabled in order to reduce input power.
Removed for creepage distance.
PFBHV
High voltage PFC feedback input. An external resistor divider is used to sense the PFC bulk voltage. The
divider high side resistor chain from the PFC bulk voltage connects to this pin. An internal high−voltage
switch disconnects the high side resistor chain from the low side resistor when the PFC is disabled in
order to reduce input power.
7
8
QCT
Fault
9
PSTimer
10
11
12
13
14
15
16
17
18
QFB
QZCD
VCC
QCS
QDRV
PDRV
PCS/PZCD
GND
PFBLV
19
20
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4
NCP1937
Table 2. NCP1937 DEVICE OPTIONS
Overload
Protection
Auto−Recovery
Auto−Recovery
Auto−Recovery
Auto−Recovery
Auto−Recovery
Auto−Recovery
Latch
Latch
Latch
PFC
Disable
Time
0.5 s
0.5 s
4s
0.5 s
0.5 s
4s
0.5 s
13 s
4s
PFC
Frequency
Clamp
250 kHz
131 kHz
131 kHz
250 kHz
131 kHz
131 kHz
250 kHz
131 kHz
131 kHz
SOIC−20
(Pb−Free)
2500 / Tape
& Reel
Device
NCP1937A1DR2G
NCP1937A2DR2G
NCP1937A3DR2G
NCP1937B1DR2G
NCP1937B2DR2G
NCP1937B3DR2G
NCP1937C1DR2G
NCP1937C4DR2G
NCP1937C61DR2G
Fault OTP
Latch
Latch
Latch
Auto−Recovery
Auto−Recovery
Auto−Recovery
Latch
Latch
Latch
V
BO(start)
111 V
111 V
111 V
111 V
111 V
111 V
111 V
111 V
101 V
V
BO(stop)
97 V
97 V
97 V
97 V
97 V
97 V
97 V
97 V
87 V
Package
Shipping
†
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
Table 3. MAXIMUM RATINGS
(Notes 1 − 6)
Rating
High Voltage Startup Circuit Input Voltage
High Voltage Startup Circuit Input Current
High Voltage Brownout Detector Input Voltage
High Voltage Brownout Detector Input Current
PFC High Voltage Feedback Input Voltage
PFC High Voltage Feedback Input Current
PFC Low Voltage Feedback Input Voltage
PFC Low Voltage Feedback Input Current
PFC Zero Current Detection and Current Sense Input Voltage (Note 1)
PFC Zero Current Detection and Current Sense Input Current
PFC Control Input Voltage
PFC Control Input Current
Supply Input Voltage
Supply Input Current
Supply Input Voltage Slew Rate
Fault Input Voltage
Fault Input Current
QR Flyback Zero Current Detection Input Voltage
QR Flyback Zero Current Detection Input Current
Pin
1
1
3
3
20
20
18
18
16
16
5
5
12
12
12
8
8
11
11
Symbol
V
HV/X2
I
HV/X2
V
BO/X2
I
BO/X2
V
PFBHV
I
PFBHV
V
PFBLV
I
PFBLV
V
PCS/PZCD
I
PCS/PZCD
V
PControl
I
PControl
V
CC(MAX)
I
CC(MAX)
dV
CC
/dt
V
Fault
I
Fault
V
QZCD
I
QZCD
Value
−0.3 to 700
20
−0.3 to 700
20
−0.3 to 700
0.5
−0.3 to 9
0.5
−0.3 to
V
PCS/PZCD(MAX)
−2/+5
−0.3 to 5
10
−0.3 to 30
30
1
−0.3 to (V
CC
+ 1.25)
10
−0.9 to (V
CC
+ 1.25)
−2/+5
Unit
V
mA
V
mA
V
mA
V
mA
V
mA
V
mA
V
mA
V/ms
V
mA
V
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. V
PCS/PZCD(MAX)
is the maximum voltage of the pin shown in the electrical table. When the voltage on this pin exceeds 5 V, the pin sinks
a current equal to (V
PCS/PZCD
− 5 V) / (2 kW). A V
PSC/PZCD
of 7 V generates a sink current of approximately 1 mA.
2. Maximum driver voltage is limited by the driver clamp voltage, V
XDRV(high)
, when V
CC
exceeds the driver clamp voltage. Otherwise, the
maximum driver voltage is V
CC
.
3. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond
those indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied.
Functional operation should be restricted to the Recommended Operating Conditions.
4. This device contains Latch−Up protection and exceeds
±
100 mA per JEDEC Standard JESD78.
5. Low Conductivity Board. As mounted on 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm
2
of 2 oz copper traces and heat
spreading area. As specified for a JEDEC51−1 conductivity test PCB. Test conditions were under natural convection of zero air flow.
6. Pins 1, 3, and 20 are rated to the maximum voltage of the part, or 700 V.
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