July 1996
NDS331N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications in notebook computers, portable phones, PCMCIA
cards, and other
battery powered circuits where fast
switching, and low in-line power loss are needed in a very
small outline surface mount package.
Features
1.3 A, 20 V. R
DS(ON)
= 0.21
Ω
@ V
GS
= 2.7 V
R
DS(ON)
= 0.16
Ω
@ V
GS
= 4.5 V.
Industry standard outline SOT-23 surface mount package
using poprietary SuperSOT
TM
-3 design for superior thermal
and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
_______________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
T
J
,T
STG
Parameter
Drain-Source Voltage
T
A
= 25°C unless otherwise noted
NDS331N
20
8
(Note 1a)
Units
V
V
A
W
Gate-Source Voltage - Continuous
Maximum Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
1.3
10
0.5
0.46
-55 to 150
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
(Note 1a)
250
(Note 1)
°C/W
°C/W
Thermal Resistance, Junction-to-Case
75
© 1997 Fairchild Semiconductor Corporation
NDS331N Rev.E
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
I
DSS
I
GSSF
I
GSSR
V
GS(th)
R
DS(ON)
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
V
GS
= 0 V, I
D
= 250 µA
V
DS
= 16 V, V
GS
= 0 V
T
J
=125°C
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
V
GS
= 8 V, V
DS
= 0 V
V
GS
= -8 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= 250 µA
T
J
=125°C
Static Drain-Source On-Resistance
V
GS
= 2.7 V, I
D
= 1.3 A
T
J
=125°C
V
GS
= 4.5 V, I
D
= 1.5 A
I
D(ON)
g
FS
C
iss
C
oss
C
rss
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
On-State Drain Current
V
GS
= 2.7 V, V
DS
= 5 V
V
GS
= 4.5 V, V
DS
= 5 V
Forward Transconductance
V
DS
= 5 V, I
D
= 1.3 A,
V
DS
= 10 V, V
GS
= 0 V,
f = 1.0 MHz
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
162
85
28
pF
pF
pF
3
4
3.5
S
0.5
0.3
0.7
0.53
0.15
0.24
0.11
20
1
10
100
-100
V
µA
µA
nA
nA
ON CHARACTERISTICS
(Note 2)
Gate Threshold Voltage
1
0.8
0.21
0.4
0.16
A
V
Ω
SWITCHING CHARACTERISTICS
(Note 2)
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= 5 V, I
D
= 1.3 A,
V
GS
= 4.5 V
V
DD
= 5 V, I
D
= 1 A,
V
GS
= 5 V, R
Gen
= 6
Ω
5
25
10
5
3.5
0.3
1
20
40
20
20
5
ns
ns
ns
ns
nC
nC
nC
NDS331N Rev.E
Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
I
SM
V
SD
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
Maximum Continuous Drain-Source Diode Forward Current
Maximum Pulsed Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 0.42 A
(Note 2)
0.8
0.42
10
1.2
A
A
V
P
D
(
t
) =
R
θ
J A
t
)
(
T
J
−
T
A
=
R
θ
J C
R
θ
CA
t
)
+
(
T
J
−
T
A
=
I
2
(
t
) ×
R
DS
(
ON
)
D
T
J
Typical R
θ
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 250
o
C/W when mounted on a 0.02 in
2
pad of 2oz copper.
b. 270
o
C/W when mounted on a 0.001 in
2
pad of 2oz copper.
1a
1b
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS331N Rev.E
Typical Electrical Characteristics
4
I
D
, DRAIN-SOURCE CURRENT (A)
1.75
3.0
3
2.7
2.0
R
DS(on)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
V
GS
=4.5V
2.5
1.5
V
GS
= 2.0V
1.25
2
2.5
1
1.5
1
2.7
3.0
3.5
4.5
0.75
0
0.5
0
V
DS
1
2
, DRAIN-SOURCE VOLTAGE (V)
3
0
0.5
I
1
D
1.5
2
, DRAIN CURRENT (A)
2.5
3
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation
with Drain Current and Gate Voltage.
1.8
DRAIN-SOURCE ON-RESISTANCE
DRAIN-SOURCE ON-RESISTANCE
1.6
1.4
1.2
1
0.8
0.6
-50
1.75
R
DS(ON)
, NORMALIZED
R
DS(on)
, NORMALIZED
I
D
= 1.3A
V
GS
= 2.7V
V
GS
= 2.7 V
1.5
TJ = 125°C
1.25
25°C
1
0.75
-55°C
0.5
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
0
0.5
1
1.5
2
I , DRAIN CURRENT (A)
D
2.5
3
Figure 3. On-Resistance Variation
with Temperature
.
Figure 4. On-Resistance Variation
with Drain Current and Temperature
.
4
1.3
GATE-SOURCE THRESHOLD VOLTAGE
V
DS
= 5.0V
I
D
, DRAIN CURRENT (A)
3
T = -55°C
J
25°C
125°C
V
th
, NORMALIZED
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
-50
V
DS
= V
GS
I
D
= 250µA
2
1
0
0
0.5
V
GS
1
1.5
2
, GATE TO SOURCE VOLTAGE (V)
2.5
3
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
Figure 5. Transfer Characteristics
.
Figure 6. Gate Threshold Variation
with Temperature
.
NDS331N Rev.E
Typical Electrical Characteristics
(continued)
BV
DSS
, NORMALIZED
DRAIN-SOURCE BREAKDOWN VOLTAGE
1.12
1
I
D
= 250µA
1.08
I , REVERSE DRAIN CURRENT (A)
V
GS
= 0V
0.1
T = 125°C
J
0.01
1.04
25°C
-55°C
1
0.96
0.001
S
0.92
-50
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
0.0001
0
0.2
0.4
0.6
0.8
1
V , BODY DIODE FORWARD VOLTAGE (V)
SD
1.2
Figure 7. Breakdown Voltage Variation with
Temperature.
Figure 8. Body Diode Forward Voltage Variation with
Source Current and Temperature
.
600
V
GS
, GATE-SOURCE VOLTAGE (V)
400
200
100
50
5
I
D
= 1.3A
4
V
DS
= 5V
15V
10V
CAPACITANCE (pF)
C iss
C oss
3
2
C rss
20
10
0.1
f = 1 MHz
V
GS
= 0V
0.2
V
DS
1
0
0.5
1
2
5
, DRAIN TO SOURCE VOLTAGE (V)
10
20
0
1
2
3
Q
g
, GATE CHARGE (nC)
4
5
Figure 9. Capacitance Characteristics
.
Figure 10. Gate Charge Characteristics
.
V
DD
V
IN
D
t
on
t
off
t
r
90%
R
L
V
OUT
t
d(on)
t
d(off)
90%
t
f
V
GS
R
GEN
V
OUT
G
DUT
10%
10%
INVERTED
90%
S
V
IN
10%
50%
50%
PULSE WIDTH
Figure 11. Switching Test Circuit
.
Figure 12. Switching Waveforms
.
NDS331N Rev.E
微控制器 MCU
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