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CY2548C004T

产品描述Clock Generators & Support Products PREMIS SSCG EMI REDUCTION
产品类别半导体    模拟混合信号IC   
文件大小342KB,共17页
制造商Cypress(赛普拉斯)
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CY2548C004T概述

Clock Generators & Support Products PREMIS SSCG EMI REDUCTION

CY2548C004T规格参数

参数名称属性值
Product AttributeAttribute Value
制造商
Manufacturer
Cypress(赛普拉斯)
产品种类
Product Category
Clock Generators & Support Products
类型
Type
Programmable Clock Generators

文档预览

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CY2544/CY2546/CY2548
Quad-PLL Programmable Clock Generator
with Spread Spectrum
Quad-PLL Programmable Clock Generator with Spread Spectrum
Features
Glitch free outputs while frequency switching
24-pin QFN package
Commercial and Industrial temperature ranges
One-time programmability
For programming support, contact
Cypress technical support
or send an e-mail to
clocks@cypress.com
Four fully-integrated phase-locked loops (PLLs)
Input frequency range
External crystal: 8 to 48 MHz for CY2544 and CY2546
External reference: 8 to 166 MHz clock
Reference clock input voltage range
2.5 V, 3.0 V, and 3.3 V for CY2548
1.8 V for CY2544 and CY2546
Wide operating output frequency range
3 to 166 MHz
Programmable spread spectrum with center and down spread
option and Lexmark and Linear modulation profiles
V
DD
supply voltage options:
2.5 V, 3.0 V, and 3.3 V for CY2544 and CY2548
1.8 V for CY2546
Selectable output clock voltages:
1.8 V, 2.5 V, 3.0 V, and 3.3 V for CY2544 and CY2548
1.8 V for CY2546
Frequency select feature with option to select eight different
frequencies over nine clock outputs
Power down, output enable, and SS ON/OFF controls
Low jitter, high accuracy outputs
Ability to synthesize nonstandard frequencies with Fractional-N
capability
Up to nine clock outputs with programmable drive strength
Benefits
Multiple high-performance PLLs allow synthesis of unrelated
frequencies
Nonvolatile programming for personalization of PLL
frequencies, spread spectrum characteristics, drive strength,
crystal load capacitance, and output frequencies
Application specific programmable EMI reduction using spread
spectrum for clocks
Programmable PLLs for system frequency margin tests
Meets critical timing requirements in complex system designs
Suitability for PC, consumer, portable, and networking
applications
Capable of Zero PPM frequency synthesis error
Uninterrupted system operation during clock frequency switch
Application compatibility in standard and low-power systems
Functional Description
For a complete list of related documentation, click
here.
Logic Block Diagram
CLKIN
Crossbar
Switch
OSC
PLL1
Output
Dividers
and
Bank
2
CLK1
Bank
1
XIN/
EXCLKIN
XOUT
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
FS 0
FS 1
FS 2
MUX
and
Control
Logic
PLL2
Drive
Strength
Control
Bank
PLL3
(SS)
3
CLK8
CLK9
PLL4
(SS)
SSON
PD#/OE
Cypress Semiconductor Corporation
Document Number: 001-12563 Rev. *M
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised October 31, 2017

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