) ............................................... -40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................ -65°C to +150°C
Lead Temperature (soldering, 10s) ................................. +300°C
Soldering Temperature (reflow)
Lead (Pb)-free packages .............................................+260°C
Packages containing lead (Pb)....................................+240°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(Typical
Operating Circuit,
V
V+
= 2.5V to 5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.) (Note 1)
PARAMETER
Operating Supply Voltage
Shutdown Supply Current
SYMBOL
V
+
I
SHDN
All digital inputs at
V+ or GND
T
A
= +25°C
T
A
= -40°C to +85°C
T
MIN
to T
MAX
180
CONDITIONS
MIN
2.5
5.5
TYP
MAX
5.5
8
10
11
240
260
280
170
210
230
240
110
135
140
145
0.7 x
V+
0.3 x
V+
GPIO inputs without pullup,
V
PORT
= V+ to GND
V
V+
= 2.5V
V
V+
= 5.5V
-100
12
80
±1
19
120
0.3
+100
30
180
µA
µA
µA
µA
UNITS
V
Operating Supply Current
I
GPOH
All ports programmed T
A
= +25°C
as outputs high, no
T
A
= -40°C to +85°C
load, all other inputs
at V+ or GND
T
MIN
to T
MAX
All ports programmed T
A
= +25°C
as outputs low, no
T
A
= -40°C to +85°C
load, all other inputs
at V+ or GND
T
MIN
to T
MAX
All ports programmed
T
A
= +25°C
as inputs without
pullup, ports, and all T
A
= -40°C to +85°C
other inputs at V+ or
T
MIN
to T
MAX
GND
Operating Supply Current
I
GPOL
Operating Supply Current
I
GPI
INPUTS AND OUTPUTS
Logic High Input Voltage
Port Inputs
Logic Low Input Voltage
Port Inputs
Input Leakage Current
GPIO Input Internal Pullup to V+
Hysteresis Voltage GPIO Inputs
V
IH
V
IL
I
IH
, I
IL
I
PU
DV
I
V
V
nA
µA
V
www.maximintegrated.com
Maxim Integrated
│
2
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
Electrical Characteristics (continued)
PARAMETER
SYMBOL
(Typical
Operating Circuit,
V
V+
= 2.5V to 5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.) (Note 1)
CONDITIONS
GPIO outputs, I
SOURCE
= 2mA,
T
A
= -40°C to +85°C
GPIO outputs, I
SOURCE
= 1mA,
T
A
= T
MIN
to T
MAX
(Note 2)
V
PORT
= 0.6V
Port configured output low, shorted to V+
MIN
V+ -
0.7
V+ -
0.7
2
2.75
0.7 x
V+
0.3 x
V+
-50
(Note 2)
V
OL
I
SINK
= 6mA
+50
10
0.4
10
11
18
20
TYP
MAX
UNITS
Output High Voltage
V
OH
I
OL
I
OLSC
V
IH
V
IL
I
IH
, I
IL
V
Port Sink Current
Output Short-Circuit Current
Input High-Voltage SDA, SCL,
AD0, AD1
Input Low-Voltage SDA, SCL,
AD0, AD1
Input Leakage Current SDA, SCL
Input Capacitance
Output Low-Voltage SDA
mA
mA
V
V
nA
pF
V
Timing Characteristics (Figure 2)
(V
V+
= 2.5V to 5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.) (Note 1)
PARAMETER
Serial Clock Frequency
Bus Free Time Between a STOP
and a START Condition
Hold Time (Repeated) START
Condition
Repeated START Condition
Setup Time
STOP Condition Setup Time
Data Hold Time
Data Setup Time
SCL Clock Low Period
SCL Clock High Period
Rise Time of Both SDA and SCL
Signals, Receiving
Fall Time of Both SDA and SCL
Signals, Receiving
Fall Time of SDA Transmitting
Pulse Width of Spike Suppressed
Capacitive Load for Each Bus
Line
SYMBOL
f
SCL
t
BUF
t
HD, STA
t
SU, STA
t
SU, STO
t
HD, DAT
t
SU, DAT
t
LOW
t
HIGH
t
R
t
F
t
F,TX
t
SP
C
b
(Notes 2, 4)
(Notes 2, 4)
(Notes 2, 5)
(Notes 2, 6)
(Note 2)
0
(Note 3)
1.3
0.6
0.6
0.6
15
100
1.3
0.7
20 +
0.1C
b
20 +
0.1C
b
20 +
0.1C
b
300
300
250
50
400
900
CONDITIONS
MIN
TYP
MAX
400
UNITS
kHz
µs
µs
µs
µs
ns
ns
µs
µs
ns
ns
ns
ns
pF
www.maximintegrated.com
Maxim Integrated
│
3
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
Timing Characteristics (Figure 2) (continued)
(V
V+
= 2.5V to 5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.) (Note 1)
Note 1:
All parameters tested at T
A
= +25°C. Specifications over temperature are guaranteed by design.
Note 2:
Guaranteed by design.
Note 3:
A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 4:
C
b
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3V+ and 0.7V+.
Note 5:
ISINK
≤ 6mA. Cb = total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3V+ and 0.7V+.
Note 6:
Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
1 Introduction
In the mid-1960s, American scientist Maas conducted extensive experimental research on the charging process of open-cell batteries and proposed an acceptable charging curve for ...[详细]
FPGA/CPLD
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