supports static lane reversal. For example, lane reversal for upstream
port A may be configured by asserting the PCI Express Port A Lane
Reverse (PEALREV) input signal or through serial EEPROM or SMBus
initialization. Lane reversal for ports B and C may be enabled via a
configuration space register, serial EEPROM, or the SMBus.
PCI Express
Slots
I/O
10GbE
I/O
10GbE
I/O
SATA
I/O
SATA
Figure 2 I/O Expansion Application
2 of 28
April 9, 2010
IDT 89HPES12N3 Data Sheet
Pin Description
The following tables list the functions of the pins provided on the PES12N3. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal
PEALREV
Type
I
Name/Description
PCI Express Port A Lane Reverse.
When this bit is asserted, the lanes of
PCI Express Port A are reversed. This value may be overridden by modify-
ing the value of the PALREV bit in the PA_SWCTL register.
PCI Express Port A Serial Data Receive.
Differential PCI Express receive
pairs for port A.
PCI Express Port A Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port A
PCI Express Port B Lane Reverse.
When this bit is asserted, the lanes of
PCI Express Port B are reversed. This value may be overridden by modify-
ing the value of the PBLREV bit in the PA_SWCTL register.
PCI Express Port B Serial Data Receive.
Differential PCI Express receive
pairs for port B.
PCI Express Port B Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port B
PCI Express Port C Lane Reverse.
When this bit is asserted, the lanes of
PCI Express Port C are reversed. This value may be overridden by modify-
ing the value of the PCLREV bit in the PA_SWCTL register.
PCI Express Port C Serial Data Receive.
Differential PCI Express receive
pairs for port C.
PCI Express Port C Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port C
PCI Express Reference Clock.
Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
PCI Express Reference Clock Mode Select.
These signals select the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Table 1 PCI Express Interface Pins
PEARP[3:0]
PEARN[3:0]
PEATP[3:0]
PEATN[3:0]
PEBLREV
I
O
I
PEBRP[3:0]
PEBRN[3:0]
PEBTP[3:0]
PEBTN[3:0]
PECLREV
I
O
I
PECRP[3:0]
PECRN[3:0]
PECTP[3:0]
PECTN[3:0]
PEREFCLKP[1:0]
PEREFCLKN[1:0]
I
O
I
REFCLKM
I
Signal
MSMBADDR[4:1]
MSMBCLK
Type
I
I/O
Name/Description
Master SMBus Address.
These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
Master SMBus Clock.
This bidirectional signal is used to synchronize
transfers on the master SMBus. This signal is active only when EEPROM
data is being loaded.
Master SMBus Data.
This bidirectional signal is used for data on the mas-
ter SMBus.
Table 2 SMBus Interface Pins (Part 1 of 2)
MSMBDAT
I/O
3 of 28
April 9, 2010
IDT 89HPES12N3 Data Sheet
Signal
SSMBADDR[5,3:1]
SSMBCLK
SSMBDAT
Type
I
I/O
I/O
Name/Description
Slave SMBus Address.
These pins determine the SMBus address to
which the slave SMBus interface responds.
Slave SMBus Clock.
This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
Slave SMBus Data.
This bidirectional signal is used for data on the slave
SMBus.
Table 2 SMBus Interface Pins (Part 2 of 2)
Signal
GPIO[0]
GPIO[1]
GPIO[2]
Type
I/O
I/O
I/O
Name/Description
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
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