NCN2612B
6-Channel Differential 1:2
Switch for PCIe 2.0 and
Display Port 1.1
The NCN2612B is a 6−Channel differential SPDT switch designed
to route PCI Express Gen2 and/or DisplayPort 1.1a signals. Due to the
ultra−low ON−state capacitance (2.1 pF typ) and resistance (8
W
typ),
this switch is ideal for switching high frequency signals up to a signal
bit rate (BR) of 5 Gbps. This switch pinout is designed to be used in
BTX form factor desktop PCs and is available in a space−saving
5x11x0.75 mm WQFN56 package. The NCN2612B uses 80% less
quiescent power than other comparable PCIe switches.
Features
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MARKING
DIAGRAM
NCN2612B
AWLYYWWG
WQFN56
CASE 510AK
A
WL
YY
WW
G
1
•
•
•
•
•
•
•
•
•
•
BTX Pinout
V
DD
Power Supply from 3 V to 3.6 V
Low Supply Current: 250
mA
typ
6 Differential Channels, 2:1 MUX/DEMUX
Compatible with Display Port 1.1a & PCIe 2.0
Data Rate: Supports 5 Gbps
Low R
ON
Resistance: 8
W
typ
Low C
ON
Capacitance: 2.1 pF
Space Saving, Small WQFN−56 Package
This is a Pb−Free Device
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
NCN2612BMTTWG
Package
WQFN56
(Pb−Free)
Shipping
†
2000 /
Tape & Reel
Typical Applications
•
Notebook Computers
•
Desktop Computers
•
Server/Storage Networks
Graphics and
Memory
Controller Hub
(GMCH)
PCIe BUFF1
PCIe BUFF2
PCI
Express PCIe BUFF3
Graphics
(PEG) PCIe BUFF4
PCIe IN
AUX
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
D1 +/−
D2 +/−
IN_0 +/−
IN_1 +/−
IN_2 +/−
IN_3 +/−
X +/−
OUT +/−
NCN2612B
D3 +/−
HPD1/HPD2
AUX +/−
Tx0 +/−
Tx1 +/−
Tx2 +/−
Tx3 +/−
Rx0 +/−
Rx1 +/−
Display Port Connector
D0 +/−
Figure 1. Application Schematic
PCIe Graphics (PEG) Connector
©
Semiconductor Components Industries, LLC, 2011
August, 2011
−
Rev. 0
1
Publication Order Number:
NCN2612B/D
NCN2612B
IN_0+
IN_0−
IN_1+
IN_1−
IN_2+
IN_2−
IN_3+
IN_3−
D0+
D0−
D1+
D1−
D2+
D2−
D3+
D3−
Tx0+
Tx0−
Tx1+
Tx1−
Tx2+
Tx2−
Tx3+
Tx3−
OUT+
OUT−
X+
X−
AUX+
AUX−
HPD1
HPD2
Rx0+
Rx0−
Rx1+
Rx1−
SEL
LE
Logic Control
Figure 2. NCN2612B Block Diagram
TRUTH TABLE (SEL Control)
Function
PCI Express Gen2 Path is Active (Tx, Rx)
Digital Video Port is Active (D, HPD, AUX)
SEL
L
H
TRUTH TABLE (Latch Control)
LE
L
H
Internal Mux Select
Respond to Changes on SEL
Latched
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2
NCN2612B
56 GND
49 GND
48 GND
47 D2+
46 D2−
45 D3+
44 D3−
43 Tx0+
42 Tx0−
41 Tx1+
40 Tx1−
Exposed Pad on
Underside
(solder to external
Gnd)
39 Tx2+
38 Tx2−
37 Tx3+
36 Tx3−
35 GND
34 VDD
33 AUX+
32 AUX−
31 HPD1
30 HPD2
29 GND
GND 21
VDD 22
Rx1− 23
Rx1+ 24
Rx0− 25
Rx0+ 26
VDD 27
GND 28
55 VDD
50 VDD
53 D0−
51 D1−
54 D0+
52 D1+
3
GND
SEL
LE
IN_0+
IN_0−
VDD
IN_1+
IN_1−
IN_2+
1
2
3
4
5
6
7
8
9
IN_2− 10
GND
IN_3+
11
12
IN_3− 13
OUT+
14
OUT− 15
GND
VDD
X+
16
17
18
X− 19
GND
20
Figure 3. Pinout
(Top View)
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NCN2612B
PIN FUNCTION AND DESCRIPTION
Pin
6, 17, 22, 27,
34,50, 55
1, 11, 16, 20, 21,
28, 29, 35, 48,
49, 56
Exposed Pad
2
3
4
5
7
8
9
10
12
13
14
15
18
19
Name
VDD
GND
DC Supply, 3.3 V
$10%
Power Ground.
Description
−
SEL
LE
IN_0+
IN_0−
IN_1+
IN_1−
IN_2+
IN_2−
IN_3+
IN_3−
OUT+
OUT−
X+
X−
The exposed pad on the backside of package is internally connected to Gnd. Externally the exposed
pad should also be user−connected to GND.
SEL controls the mux through a flow−through latch. Do not float this pin.
SEL = 0 for PCIE Mode; SEL = 1 for DP Mode
LE controls the latch gate. Do not float this pin.
Differential input from GMCH PCIE outputs. IN_0+ makes a differential pair with IN_0−.
Differential input from GMCH PCIE outputs. IN_0− makes a differential pair with IN_0+.
Differential input from GMCH PCIE outputs. IN_1+ makes a differential pair with IN_1−.
Differential input from GMCH PCIE outputs. IN_1− makes a differential pair with IN_1+.
Differential input from GMCH PCIE outputs. IN_2+ makes a differential pair with IN_2−.
Differential input from GMCH PCIE outputs. IN_2− makes a differential pair with IN_2+.
Differential input from GMCH PCIE outputs. IN_3+ makes a differential pair with IN_3−.
Differential input from GMCH PCIE outputs. IN_3− makes a differential pair with IN_3+.
Pass−through output from AUX+ input when SEL = 1. Pass−through output from Rx0+ input when
SEL = 0.
Pass−through output from AUX− input when SEL = 1. Pass−through output from Rx0− input when
SEL = 0.
X+ is an analog pass−through output corresponding to Rx1+.
X− is an analog pass−through output corresponding to the Rx1− input. The path
from Rx1− to X− must be matched with the path from Rx1+ to X+. X+ and X− form a
differential pair when the pass−through mux mode is selected.
Differential input from PCIE connector or device. Rx1− makes a differential pair with Rx1+. Rx1− is
passed through to the X− pin on the path that matches the Rx1+ to X+ pin.
Differential input from PCIE connector or device. Rx1+ makes a differential pair with Rx1−. Rx1+ is
passed through to the X+ pin when SEL = 0.
Differential input from PCIE connector or device. Rx0− makes a differential pair with Rx0+. Rx0− is
passed through to the OUT− pin when SEL = 0.
Differential input from PCIE connector or device. Rx0+ makes a differential pair with Rx0−. Rx0+ is
passed through to the OUT+ pin when SEL = 0.
Negative low frequency HPD input handshake protocol signal (normally not connected).
Positive low frequency HPD input handshake protocol signal.
Differential input from HDMI/DP connector. AUX− makes a differential
pair with AUX+. AUX− is passed through to the OUT− pin when SEL = 1.
Differential input from HDMI/DP connector. AUX+ makes a differential
pair with AUX−. AUX+ is passed through to the OUT+ pin when SEL = 1.
Analog pass−through output#2 corresponding to IN_3+ and IN_3− when SEL = 0.
Analog pass−through output#2 corresponding to IN_2+ and IN_2− when SEL = 0.
Analog pass−through output#2 corresponding to IN_1+ and IN_1− when SEL = 0.
Analog pass−through output#2 corresponding to IN_0+ and IN_0− when SEL = 0.
Analog pass−through output#1 corresponding to IN_3+ and IN_3−, when SEL = 1.
Analog pass−through output#1 corresponding to IN_2+ and IN_2−, when SEL = 1.
Analog pass−through output#1 corresponding to IN_1+ and IN_1−, when SEL = 1.
Analog pass−through output#1 corresponding to IN_0+ and IN_0−, when SEL = 1.
23
24
25
26
30
31
32
33
37, 36
39, 38
41, 40
43, 42
45, 44
47, 46
52, 51
54, 53
Rx1−
Rx1+
Rx0−
Rx0+
HPD2
HPD1
AUX−
AUX+
Tx3+, Tx3−
Tx2+, Tx2−
Tx1+, Tx1−
Tx0+, Tx0−
D3+, D3−
D2+, D2−
D1+, D1−
D0+, D0−
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4
NCN2612B
MAXIMUM RATINGS
Parameter
Power Supply Voltage
Input/Output Voltage Range of the Switch
(Tx, Rx, D, HPD, AUX, IN_, OUT, X)
Selection Pin Voltages (SEL and LE)
Continuous Current Through One Switch Channel
Maximum Junction Temperature (Note 1)
Operating Ambient Temperature
Storage Temperature Range
Thermal Resistance, Junction−to−Air (Note 2)
Latch−up Current (Note 3)
Human Body Model (HBM) ESD Rating (Note 4)
Machine Model (MM) ESD Rating (Note 4)
Moisture Sensitivity (Note 5)
Symbol
V
DD
V
IS
V
IN
I
IS
T
J
T
A
T
stg
R
qJA
I
LU
ESD HBM
ESD MM
MSL
Rating
−0.5
to 5.3
−0.5
to V
DD
+ 0.3
−0.5
to V
DD
+ 0.3
±120
150
−40
to +85
−65
to +150
37
±100
7000
400
Level 1
Unit
V
DC
V
DC
V
DC
mA
°C
°C
°C
°C/W
mA
V
V
−
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Power dissipation must be considered to ensure maximum junction temperature (T
J
) is not exceeded.
2. This parameter is based on EIA/JEDEC 51−7 with a 4−layer PCB, 80 mm x 80 mm, two 1oz Cu material internal planes and top planes of
2oz Cu material.
3. Latch up Current Maximum Rating:
±100
mA per JEDEC standard: JESD78.
4. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM)
±7.0
kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM)
±400
V per JEDEC standard: JESD22−A115 for all pins.
5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
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