TDA8037
Low power 3V smart card interface
Rev. 1.2 — 30 June 2016
Product data sheet
1. General description
The TDA8037 is the cost efficient successor of the established integrated contact smart
card reader IC TDA8035. It offers a high level of security for the card performing current
limitation, short circuit detection, ESD protection as well as supply supervision. Operating
in 3 V supply domain, the current consumption during the shutdown mode of the contact
reader is very low. It is therefore the ideal component for a power efficient contact reader.
2. Features and benefits
2.1 Protection of the contact smart card
Thermal and short-circuit protection on all card contacts
V
CC
regulation:
3 V
5 % on 2
220 nF multilayer ceramic capacitors with low ESR
Current spikes of 40 nA up to 20 MHz, with controlled rise and fall times, filtered
overload detection approximately 120 mA
Automatic activation and deactivation sequences initiated by software or by hardware
in the event of a short-circuit, card take-off, overheating, V
DDhost
, VREG and V
DD
dropping
Enhanced card-side ElectroStatic Discharge (ESD) protection of (> 8 kV)
Supply supervisor for killing spikes during power on and off:
threshold internally fixed
externally by a resistor bridge (with SO28 package only)
2.2 Easy integration into your contact reader
SW compatible to TDA8024, TDA8034 and TDA8035
3 V smart card supply
Three protected half-duplex bidirectional buffered I/O lines (C4, C7 and C8)
External clock input up to 20 MHz
Card clock generation up to 20 MHz using pin CLKDIV with synchronous frequency
changes of f
CLKIN
, f
CLKIN
/2 (with SO28 package only)
Non-inverted control of pin RST using pin RSTIN
Built-in debouncing on card presence contact
Multiplexed status signal using pin OFFN
Chip Select digital input for parallel operation of several TDA8037 ICs (with SO28
package only)
NXP Semiconductors
TDA8037
Low power 3V smart card interface
2.2.1 Other
TSSOP16 and SO28 package
SO28 version is footprint compatible with TDA8024T
Compliant with ISO 7816, Cisco technology and EMV 4.3 payment systems
3. Applications
Pay TV
Electronic payment
Identification
IC card readers for banking
4. Quick reference data
Table 1.
Quick reference data
V
DDP
= 3.3 V; V
DD(INTF)
= 3.3 V; f
Xtal
= 10 MHz; GND = 0 V; T
amb
= 25
C; unless otherwise specified
Symbol
Supply
V
DD
I
DD
supply voltage
supply current
Shutdown mode;
f
CLKIN
= stopped
active mode; CLK = CLKIN;
no-load
active mode; CLK = CLKIN;
I
CC
= 65 mA
Supply voltage for the card: pin V
CC
V
CC
V
ripple(p-p)
I
CC
General
t
deact
P
tot
T
amb
deactivation time
total power dissipation
ambient temperature
total sequence
T
amb
=
25 C
to +85
C
35
-
25
90
-
-
250
0.1
+85
s
W
C
supply voltage
peak-to-peak ripple voltage
supply current
DC I
CC
< 65 mA
AC current spikes of 40 nA
from 20 kHz to 200 MHz
2.85
2.76
-
-
-
-
-
-
3.15
3.24
150
65
V
V
mV
mA
-
-
-
-
5
70
mA
mA
3
-
3.3
250
3.6
400
V
A
Parameter
Conditions
Min
Typ
Max
Unit
5. Ordering information
Table 2.
Ordering information
Package
Name
TDA8037TT
TDA8037T
TSSOP16
SO28
Description
plastic thin shrink small outline package; 16 leads; body width
4.4 mm
plastic small outline package; 28 leads; body width 7.5 mm
Version
SOT403-1
SOT136-1
Type number
TDA8037
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1.2 — June 30, 2016
2 of 29
NXP Semiconductors
TDA8037
Low power 3V smart card interface
6. Block diagram
V
DD
V
DDhost
10 µF
100 nF
PORADJ
V
DD
CS
GND
V
DD
TEST
INTERNAL
REGULATOR
CMDVCCN
reset and
supalarm
V
CC
2x
220 nF
CLKDIV
LATCH
input
sense
SUPERVISOR
RSTIN
RST
BANDGAP
HOST
INTERFACE
I/OUC
UC
AUX1UC
AUX2UC
interruption
HZ
configurations
bus for smartcard THERMAL PROTECTION
reader interface
DIGITAL
SEQUENCER
INTERNAL OSCILLATOR
ISO7816
READER
INTERFACE
AUX1
AUX2
CLK
CARD
CONNECTOR
c5
c6
c7
c1
c2
c3
c4
I/O
c8
VDD
CLOCK CIRCUITRY
CLKIN
HZ
OFFN
TDA8037
PRESN
aaa-011372
Fig 1. Block diagram
TDA8037
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1.2 — June 30, 2016
3 of 29
NXP Semiconductors
TDA8037
Low power 3V smart card interface
7. Pinning information
7.1 Pinning
AUX1UC
AUX2UC
V
DD
PRESN
I/O
AUX2
AUX1
GND
1
2
3
4
5
6
7
8
aaa-011373
16 I/OUC
15 CLKIN
14 OFFN
13 RSTIN
12 CMDVCCN
11 V
CC
10 RST
9
CLK
TDA8037TT
Fig 2.
Pin configuration TSSOP16
7.2 Pinning
CLKDIV
n.c.
n.c.
TEST
n.c.
V
DD
n.c.
n.c.
PRESN
1
2
3
4
5
6
7
8
9
28 AUX2UC
27 AUX1UC
26 I/OUC
25 n.c.
24 CLKIN
23 OFFN
22 n.c.
21 CS
20 RSTIN
19 CMDVCCN
18 PORADJ
17 V
CC
16 RST
15 CLK
aaa-011374
TDA8037T
n.c. 10
I/O 11
AUX2 12
AUX1 13
GND 14
Fig 3.
Pin configuration SO28
TDA8037
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1.2 — June 30, 2016
4 of 29
NXP Semiconductors
TDA8037
Low power 3V smart card interface
7.3 Pin description
Table 3.
Symbol
AUX1UC
AUX2UC
V
DD
PRESN
Pin description
Pin
Pin
SO28 TSSOP16
27
28
6
9
1
2
3
4
Supply
V
DD
V
DD
V
DD
V
DD
Type
I/O
I/O
supply
I
Description
auxiliary data line to/from the host (internal 10 k pull-up resistor
to V
DD
)
auxiliary data line to/from the host (internal 10 k pull-up resistor
to V
DD
)
supply voltage
card presence contact input (active LOW); if PRESN is true, then
the card is considered as present. A debouncing feature of
4.05 ms typ. is built in.
data line to/from the card (C7)(internal 10 k pull up resistor to
V
CC
)
auxiliary data line to/from the card (C8) (internal 10 k pull up
resistor to
V
CC
)
auxiliary data line to/from the card (C4) (internal 10 k pull up
resistor to
V
CC
)
ground
clock to the card (C3)
card reset (C2)
supply for the card (C1) (decouple to GND with 2x 220 nF
capacitors with ESR<100 m).
start activation sequence input from the host (active LOW)
card reset input from the host (active HIGH)
NMOS interrupt to the host (active LOW) with 10 k internal
pull-up resistor to V
DD
(see fault detection)
external clock
host data I/O line (internal 10k pull-up resistor to V
DD
)
control for choosing CLK frequency
test mode
input for V
DDhost
supervisor. PORADJ threshold can be changed
with an external R bridge.
chip select input from the host (active High)
I/O
AUX2
AUX1
GND
CLK
RST
V
CC
CMDVCCN
RSTIN
OFFN
CLKIN
I/OUC
CLKDIV
TEST
PORADJ
CS
11
12
13
14
15
16
17
19
20
23
24
26
1
4
18
21
5
6
7
8
9
10
11
12
13
14
15
16
nc
nc
nc
nc
V
CC
V
CC
V
CC
-
V
CC
V
CC
V
CC
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
I/O
I/O
I/O
supply
O
O
O
I
I
O
I
I/O
I
I
I
I
TDA8037
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1.2 — June 30, 2016
5 of 29
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
