Programmable System-on-Chip (PSoC )
General Description
PSoC
®
3: CY8C32 Family Data Sheet
®
PSoC
®
3 is a true programmable embedded system-on-chip, integrating configurable analog and digital peripherals, memory, and a
microcontroller on a single chip. The PSoC 3 architecture boosts performance through:
8051 core plus DMA controller at up to 50 MHz
Ultra low power with industry's widest voltage range
Programmable digital and analog peripherals enable custom functions
Flexible routing of any analog or digital peripheral function to any pin
PSoC devices employ a highly configurable system-on-chip architecture for embedded control design. They integrate configurable
analog and digital circuits, controlled by an on-chip microcontroller. A single PSoC device can integrate as many as 100 digital and
analog peripheral functions, reducing design time, board space, power consumption, and system cost while improving system quality.
Features
Operating characteristics
Analog peripherals
Voltage range: 1.71 to 5.5 V, up to six power domains
[1]
Temperature range (ambient) –40 to 85 °C
DC to 50-MHz operation
Power modes
• Active mode 1.2 mA at 6 MHz, and 12 mA at 48 MHz
• 1-µA sleep mode
• 200-nA hibernate mode with RAM retention
Boost regulator from 0.5-V input up to 5-V output
Performance
8-bit 8051 CPU, 32 interrupt inputs
24-channel direct memory access (DMA) controller
Configurable 8- to 12-bit delta-sigma ADC
8-bit DAC
Two comparators
®
CapSense support, up to 62 sensors
1.024 V ±1% internal voltage reference
Versatile I/O system
Memories
Up to 64 KB program flash, with cache and security features
Up to 8 KB additional flash for error correcting code (ECC)
Up to 8 KB RAM
Up to 2 KB EEPROM
Digital peripherals
Four 16-bit timer, counter, and PWM (TCPWM) blocks
2
I C, 1 Mbps bus speed
USB 2.0 certified Full-Speed (FS) 12 Mbps peripheral
interface (TID#40770053) using internal oscillator
[2]
16 to 24 universal digital blocks (UDB), programmable to
create any number of functions:
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• I
2
C, UART, SPI, I2S, LIN 2.0 interfaces
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generators
• Quadrature decoders
• Gate-level logic functions
29 to 72 I/O pins – up to 62 general-purpose I/Os (GPIOs)
Up to eight performance I/O (SIO) pins
• 25 mA current sink
• Programmable input threshold and output high voltages
• Can act as a general-purpose comparator
• Hot swap capability and overvoltage tolerance
Up to two USBIO pins that can be used as GPIOs
Route any digital or analog peripheral to any GPIO
LCD direct drive from any GPIO, up to 46 × 16 segments
CapSense support from any GPIO
1.2-V to 5.5-V interface voltages, up to four power domains
Programming and debug
JTAG (4-wire), serial wire debug (SWD) (2-wire), and single
wire viewer (SWV) interfaces
2
Bootloader programming through I C, SPI, UART, USB, and
other interfaces
Package options: 48-pin SSOP, 48-pin QFN, 68-pin QFN,
Programmable clocking
3- to 24-MHz internal oscillator, 2% accuracy at 3 MHz
4- to 25-MHz external crystal oscillator
Internal PLL clock generation up to 50 MHz
Low-power internal oscillator at 1, 33, and 100 kHz
32.768-kHz external watch crystal oscillator
12 clock dividers routable to any peripheral or I/O
100-pin TQFP, and 72-pin WLCSP
Development support with free PSoC Creator™ tool
Schematic and firmware design support
Over 100 PSoC Components™ integrate multiple ICs and
system interfaces into one PSoC. Components are free
embedded ICs represented by icons. Drag and drop
component icons to design systems in PSoC Creator.
Includes free Keil 8051 compiler
Supports device programming and debugging
Notes
1. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. This feature on select devices only. See
Ordering Information
on page 111 for details.
Cypress Semiconductor Corporation
Document Number: 001-56955 Rev. *Z
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 27, 2017
PSoC
®
3: CY8C32 Family Data Sheet
More Information
Cypress provides a wealth of data at
www.cypress.com
to help you to select the right PSoC device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP.
Following is an abbreviated list for PSoC 3:
Overview:
PSoC Portfolio, PSoC Roadmap
Product Selectors:
PSoC 1, PSoC 3, PSoC 4, PSoC 5LP
Development Kits:
In addition, PSoC Creator includes a device selection tool.
application notes and
code examples
covering a broad range
of topics, from basic to advanced level. Recommended appli-
cation notes for getting started with PSoC 3 are:
AN54181:
Getting Started With PSoC 3
AN61290:
Hardware Design Considerations
AN57821:
Mixed Signal Circuit Board Layout
AN58304:
Pin Selection for Analog Designs
AN81623:
Digital Design Best Practices
AN73854:
Introduction To Bootloaders
Application notes: Cypress offers a large number of PSoC
CY8CKIT-030
is designed for analog performance, for devel-
oping high-precision analog, low-power, and low-voltage ap-
plications.
CY8CKIT-001
provides a common development platform for
any one of the PSoC 1, PSoC 3, PSoC 4, or PSoC 5LP
families of devices.
The
MiniProg3
device provides an interface for flash pro-
gramming and debug.
Technical Reference Manuals (TRM)
Architecture TRM
Registers TRM
Programming Specification
PSoC Creator
PSoC Creator
is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100
pre-verified, production-ready PSoC Components; see the
list of component datasheets.
With PSoC Creator, you can:
1. Drag and drop component icons to build your hardware
3. Configure components using the configuration tools
system design in the main design workspace
4. Explore the library of 100+ components
2. Codesign your application firmware with the PSoC hardware,
5. Review component datasheets
using the PSoC Creator IDE C compiler
Figure 1. Multiple-Sensor Example Project in PSoC Creator
Document Number: 001-56955 Rev. *Z
Page 2 of 128
PSoC
®
3: CY8C32 Family Data Sheet
Contents
1. Architectural Overview ..................................................... 4
2. Pinouts ............................................................................... 6
3. Pin Descriptions .............................................................. 12
4. CPU ................................................................................... 13
4.1 8051 CPU ................................................................. 13
4.2 Addressing Modes .................................................... 13
4.3 Instruction Set .......................................................... 14
4.4 DMA and PHUB ....................................................... 18
4.5 Interrupt Controller ................................................... 20
5. Memory ............................................................................. 24
5.1 Static RAM ............................................................... 24
5.2 Flash Program Memory ............................................ 24
5.3 Flash Security ........................................................... 24
5.4 EEPROM .................................................................. 24
5.5 Nonvolatile Latches (NVLs) ...................................... 25
5.6 External Memory Interface ....................................... 26
5.7 Memory Map ............................................................ 26
6. System Integration .......................................................... 28
6.1 Clocking System ....................................................... 28
6.2 Power System .......................................................... 31
6.3 Reset ........................................................................ 36
6.4 I/O System and Routing ........................................... 37
7. Digital Subsystem ........................................................... 45
7.1 Example Peripherals ................................................ 45
7.2 Universal Digital Block .............................................. 47
7.3 UDB Array Description ............................................. 50
7.4 DSI Routing Interface Description ............................ 50
7.5 USB .......................................................................... 52
7.6 Timers, Counters, and PWMs .................................. 52
7.7 I
2
C ............................................................................ 53
8. Analog Subsystem .......................................................... 55
8.1 Analog Routing ......................................................... 56
8.2 Delta-sigma ADC ...................................................... 58
8.3 Comparators ............................................................. 59
8.4 LCD Direct Drive ...................................................... 60
8.5 CapSense ................................................................. 61
8.6 Temp Sensor ............................................................ 61
8.7 DAC .......................................................................... 61
9. Programming, Debug Interfaces, Resources ................ 62
9.1 JTAG Interface ......................................................... 62
9.2 Serial Wire Debug Interface ..................................... 64
9.3 Debug Features ........................................................ 65
9.4 Trace Features ......................................................... 65
9.5 Single Wire Viewer Interface .................................... 65
9.6 Programming Features ............................................. 65
9.7 Device Security ........................................................ 65
9.8 CSP Package Bootloader ......................................... 66
10. Development Support ................................................... 66
10.1 Documentation ....................................................... 66
10.2 Online ..................................................................... 66
10.3 Tools ....................................................................... 66
11. Electrical Specifications ............................................... 67
11.1 Absolute Maximum Ratings .................................... 67
11.2 Device Level Specifications .................................... 68
11.3 Power Regulators ................................................... 72
11.4 Inputs and Outputs ................................................. 76
11.5 Analog Peripherals ................................................. 84
11.6 Digital Peripherals .................................................. 96
11.7 Memory .................................................................. 99
11.8 PSoC System Resources ..................................... 105
11.9 Clocking ................................................................ 107
12. Ordering Information ................................................... 111
12.1 Part Numbering Conventions ............................... 112
13. Packaging ..................................................................... 113
14. Acronyms ..................................................................... 117
15. Reference Documents ................................................. 118
16. Document Conventions .............................................. 119
16.1 Units of Measure .................................................. 119
17. Revision History .......................................................... 120
18. Sales, Solutions, and Legal Information ................... 128
Worldwide Sales and Design Support.......................... 128
Products ....................................................................... 128
PSoC® Solutions ......................................................... 128
Cypress Developer Community.................................... 128
Technical Support ........................................................ 128
Document Number: 001-56955 Rev. *Z
Page 3 of 128
PSoC
®
3: CY8C32 Family Data Sheet
1. Architectural Overview
Introducing the CY8C32 family of ultra low-power, flash Programmable System-on-Chip (PSoC
®
) devices, part of a scalable 8-bit
PSoC 3 and 32-bit PSoC 5 platform. The CY8C32 family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables
a high level of integration in a wide variety of consumer, industrial, and medical applications.
Figure 1-1. Simplified Block Diagram
Analog Interconnect
Digital Interconnect
SIO
GPIOs
System Wide
Resources
Usage Example for UDB
Xtal
Osc
Digital System
Universal Digital Block Array (24 x UDB)
Sequencer
8- Bit
Timer
UDB
Quadrature Decoder
UDB
16- Bit
PWM
UDB
16- Bit PRS
UDB
UDB
UDB
I2C
Master
/
Slave
4- 25 MHz
( Optional
)
22
UDB
UDB
8- Bit
Timer
Logic
UDB
UDB
UDB
UDB
I2C Slave
UDB
UDB
8- Bit SPI
FS USB
2.0
USB
PHY
Clock Tree
12- Bit SPI
UDB
UDB
UDB
UDB
GPIOs
IMO
Logic
UDB
UART
UDB
UDB
12- Bit PWM
UDB
UDB
UDB
GPIOs
32. 68 KHz
7
( Optional
)
RTC
Timer
System Bus
GPIOs
Memory System
WDT
and
Wake
GPIOs
EEPROM
SRAM
CPU System
8051 or
Cortex M3
CPU
Interrupt
Controller
Program &
Debug
Program
Debug &
Trace
EMIF
ILO
FLASH
PHUB
DMA
Boundary
Scan
Clocking System
GPIOs
Analog System
SIOs
Power Management
System
LCD Direct
Drive
POR and
LVD
Sleep
Power
1.71 to
5.5V
1.8V LDO
SMP
Temperature
Sensor
DAC
CapSense
ADC
1x
Del Sig
ADC
+
GPIOs
2x
CMP
-
0. 5 to 5.5V
( Optional
)
Figure 1-1
illustrates the major components of the CY8C32
family. They are:
8051 CPU subsystem
Nonvolatile subsystem
Programming, debug, and test subsystem
Inputs and outputs
Clocking
Power
Digital subsystem
Analog subsystem
PSoC’s digital subsystem provides half of its unique
configurability. It connects a digital signal from any peripheral to
any pin through the Digital System Interconnect (DSI). It also
provides functional flexibility through an array of small, fast,
low-power UDBs. PSoC Creator provides a library of prebuilt and
tested standard digital peripherals (UART, SPI, LIN, PRS, CRC,
timer, counter, PWM, AND, OR, and so on) that are mapped to
the UDB array. You can also easily create a digital circuit using
boolean primitives by means of graphical design entry. Each
UDB contains programmable array logic (PAL)/programmable
logic device (PLD) functionality, together with a small state
machine engine to support a wide variety of peripherals.
Document Number: 001-56955 Rev. *Z
Page 4 of 128
PSoC
®
3: CY8C32 Family Data Sheet
In addition to the flexibility of the UDB array, PSoC also provides
configurable digital blocks targeted at specific functions. For the
CY8C32 family these blocks can include four 16-bit timers,
counters, and PWM blocks; I
2
C slave, master, and multimaster;
and FS USB.
For more details on the peripherals see the
“Example
Peripherals”
section on page 45 of this datasheet. For
information on UDBs, DSI, and other digital blocks, see the
“Digital Subsystem”
section on page 45 of this datasheet.
PSoC’s analog subsystem is the second half of its unique
configurability. All analog performance is based on a highly
accurate absolute voltage reference with less than 1-percent
error over temperature and voltage. The configurable analog
subsystem includes:
Analog muxes
Comparators
Voltage references
ADC
DAC
exchange data without CPU involvement. This allows the CPU
to run slower (saving power) or use those CPU cycles to improve
the performance of firmware algorithms. The single cycle 8051
CPU runs ten times faster than a standard 8051 processor. The
processor speed itself is configurable, allowing you to tune active
power consumption for specific applications.
PSoC’s nonvolatile subsystem consists of flash, byte-writeable
EEPROM, and nonvolatile configuration options. It provides up
to 64 KB of on-chip flash. The CPU can reprogram individual
blocks of flash, enabling bootloaders. You can enable an ECC
for high reliability applications. A powerful and flexible protection
model secures the user's sensitive information, allowing
selective memory block locking for read and write protection. Up
to 2 KB of byte-writeable EEPROM is available on-chip to store
application data. Additionally, selected configuration options
such as boot speed and pin drive mode are stored in nonvolatile
memory. This allows settings to activate immediately after POR.
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the VDDIO pins. Every GPIO
has analog I/O, LCD drive
[3]
, CapSense
[4]
, flexible interrupt
generation, slew rate control, and digital I/O capability. The SIOs
on PSoC allow Voh to be set independently of VDDIO when used
as outputs. When SIOs are in input mode they are high
impedance. This is true even when the device is not powered or
when the pin voltage goes above the supply voltage. This makes
the SIO ideally suited for use on an I
2
C bus where the PSoC may
not be powered when other devices on the bus are. The SIO pins
also have high current sink capability for applications such as
LED drives. The programmable input threshold feature of the
SIO can be used to make the SIO function as a general purpose
analog comparator. For devices with FS USB the USB physical
interface is also provided (USBIO). When not using USB these
pins may also be used for limited digital functionality and device
programming. All of the features of the PSoC I/Os are covered
in detail in the
“I/O System and Routing”
section on page 37 of
this datasheet.
The PSoC device incorporates flexible internal clock generators,
designed for high stability and factory trimmed for high accuracy.
The Internal Main Oscillator (IMO) is the clock base for the
system, and has 2-percent accuracy at 3 MHz. The IMO can be
configured to run from 3 MHz up to 24 MHz. Multiple clock
derivatives can be generated from the main clock frequency to
meet application needs. The device provides a PLL to generate
clock frequencies up to 50 MHz from the IMO, external crystal,
or external reference clock. It also contains a separate, very
low-power Internal Low-Speed Oscillator (ILO) for the sleep and
watchdog timers. A 32.768-kHz external watch crystal is also
supported for use in RTC applications. The clocks, together with
programmable clock dividers, provide the flexibility to integrate
most timing requirements.
The CY8C32 family supports a wide supply operating range from
1.71 V to 5.5 V. This allows operation from regulated supplies
such as 1.8 ± 5 percent, 2.5 V ±10 percent, 3.3 V ± 10 percent,
or 5.0 V ± 10 percent, or directly from a wide range of battery
types. In addition, it provides an integrated high efficiency
synchronous boost converter that can power the device from
supply voltages as low as 0.5 V.
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals. The heart of the analog
subsystem is a fast, accurate, configurable delta-sigma ADC
with these features:
Less than 100 µV offset
A gain error of 0.2 percent
INL less than ±1 LSB
DNL less than ±1 LSB
SINAD better than 66 dB
This converter addresses a wide variety of precision analog
applications, including some of the most demanding sensors.
A high-speed voltage or current DAC supports 8-bit output
signals at an update rate of 8 Msps in current DAC (IDAC) and
1 Msps in voltage DAC (VDAC). It can be routed out of any GPIO
pin. You can create higher resolution voltage PWM DAC outputs
using the UDB array. This can be used to create a pulse width
modulated (PWM) DAC of up to 10 bits, at up to 48 kHz. The
digital DACs in each UDB support PWM, PRS, or delta-sigma
algorithms with programmable widths.
In addition to the ADC and DAC, the analog subsystem provides
multiple comparators.
See the
“Analog Subsystem”
section on page 55 of this
datasheet for more details.
PSoC’s 8051 CPU subsystem is built around a single cycle
pipelined 8051 8-bit processor running at up to 50 MHz. The
CPU subsystem includes a programmable nested vector
interrupt controller, DMA controller, and RAM. PSoC’s nested
vector interrupt controller provides low latency by allowing the
CPU to vector directly to the first address of the interrupt service
routine, bypassing the jump instruction required by other
architectures. The DMA controller enables peripherals to
Notes
3. This feature on select devices only. See
Ordering Information
on page 111 for details.
4. GPIOs with opamp outputs are not recommended for use with CapSense.
Document Number: 001-56955 Rev. *Z
Page 5 of 128
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