SAA7114
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI data slicer and high performance scaler
Rev. 03 — 17 January 2006
Product data sheet
1. General description
The SAA7114 is a video capture device for applications at the image port of Video
Graphics Array (VGA) controllers.
The SAA7114 is a combination of a two-channel analog preprocessing circuit including
source selection, anti-aliasing filter and Analog-to-Digital Converter (ADC), an automatic
clamp and gain control, a Clock Generation Circuit (CGC), a digital multistandard decoder
containing two-dimensional chrominance/luminance separation by an adaptive comb filter
and a high performance scaler, including variable horizontal and vertical up and
downscaling and a brightness, contrast and saturation control circuit.
It is a highly integrated circuit for desktop video and similar applications. The decoder is
based on the principle of line-locked clock decoding and is able to decode the color of
PAL, SECAM and NTSC signals into ITU 601 compatible color component values. The
SAA7114 accepts CVBS or S-video (Y/C) as analog inputs from TV or VCR sources,
including weak and distorted signals. An expansion port (X port) for digital video
(bidirectional half duplex, D1 compatible) is also supported to connect to MPEG or a video
phone codec. At the so called image port (I port) the SAA7114 supports 8-bit or 16-bit
wide output data with auxiliary reference data for interfacing to VGA controllers.
The target application for the SAA7114 is to capture and scale video images, to be
provided as a digital video stream through the image port of a VGA controller, for display
via the frame buffer of the VGA, or for capture to system memory.
In parallel the SAA7114 also incorporates provisions for capturing the serially coded data
in the Vertical Blanking Interval (VBI) data. Two principal functions are available:
1. To capture raw video samples, after interpolation to the required output data rate, via
the scaler
2. A versatile data slicer (data recovery) unit
The SAA7114 also incorporates field-locked audio clock generation. This function ensures
that there is always the same number of audio samples associated with a field, or a set of
fields. This prevents the loss of synchronization between video and audio during capture
or playback.
The circuit is I
2
C-bus controlled (full write/read capability for all programming registers, bit
rate up to 400 kbit/s).
Philips Semiconductors
SAA7114
PAL/NTSC/SECAM video decoder
2. Features
2.1 Video decoder
s
Six analog inputs, internal analog source selectors, e.g. 6
×
CVBS or (2
×
Y/C and
2
×
CVBS) or (1
×
Y/C and 4
×
CVBS)
s
Two analog preprocessing channels in differential CMOS style inclusive built-in analog
anti-alias filters
s
Fully programmable static gain or Automatic Gain Control (AGC) for the selected
CVBS or Y/C channel
s
Automatic Clamp Control (ACC) for CVBS, Y and C
s
Switchable white peak control
s
Two 9-bit video CMOS ADCs, digitized CVBS or Y/C signals are available on the
expansion port
s
On-chip line-locked clock generation in accordance with
“ITU 601”
s
Digital Phase-Locked Loop (PLL) for synchronization and clock generation from all
standards and non-standard video sources e.g. consumer grade VTR
s
Requires only one crystal (32.11 MHz or 24.576 MHz) for all standards
s
Horizontal and vertical sync detection
s
Automatic detection of 50 Hz and 60 Hz field frequency, and automatic switching
between PAL and NTSC standards
s
Luminance and chrominance signal processing for PAL B, G, D, H, I and N,
combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC 4.43 and SECAM
s
Adaptive 2/4-line comb filter for two dimensional chrominance/luminance separation:
x
Increased luminance and chrominance bandwidth for all PAL and NTSC standards
x
Reduced cross color and cross luminance artefacts
s
PAL delay line for correcting PAL phase errors
s
Independent Brightness Contrast Saturation (BCS) adjustment for decoder part
s
User programmable sharpness control
s
Independent gain and offset adjustment for raw data path
2.2 Video scaler
s
Horizontal and vertical downscaling and upscaling to randomly sized windows
s
Horizontal and vertical scaling range: variable zoom to
1
⁄
64
(icon) (it should be noted
that the H and V zoom are restricted by the transfer data rates)
s
Anti-alias and accumulating filter for horizontal scaling
s
Vertical scaling with linear phase interpolation and accumulating filter for anti-aliasing
(6-bit phase accuracy)
s
Horizontal phase correct up and downscaling for improved signal quality of scaled
data, especially for compression and video phone applications, with 6-bit phase
accuracy (1.2 ns step width)
s
Two independent programming sets for scaler part, to define two ‘ranges’ per field or
sequences over frames
s
Fieldwise switching between decoder part and expansion port (X port) input
s
Brightness, contrast and saturation controls for scaled outputs
SAA7114_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
2 of 144
Philips Semiconductors
SAA7114
PAL/NTSC/SECAM video decoder
2.3 VBI data decoder and slicer
s
Versatile VBI data decoder, slicer, clock regeneration and byte synchronization e.g. for
World Standard Teletext (WST), North American Broadcast Text System (NABTS),
closed caption, Wide Screen Signalling (WSS), etc.
2.4 Audio clock generation
s
Generation of a field-locked audio master clock to support a constant number of audio
clocks per video field
s
Generation of an audio serial and left/right (channel) clock signal
2.5 Digital I/O interfaces
s
Real-time signal port (R port), inclusive continuous line-locked reference clock and
real-time status information supporting RTC level 3.1 (refer to document
“RTC Functional Specification”
for details)
s
Bidirectional expansion port (X port) with half duplex functionality (D1), 8-bit Y-C
B
-C
R
:
x
Output from decoder part, real-time and unscaled
x
Input to scaler part, e.g. video from MPEG decoder (extension to 16-bit possible)
s
Video image port (I port) configurable for 8-bit data (extension to 16-bit possible) in
master mode (own clock), or slave mode (external clock), with auxiliary timing and
handshake signals
s
Discontinuous data streams supported
s
32-word
×
4-byte FIFO register for video output data
s
28-word
×
4-byte FIFO register for decoded VBI data output
s
Scaled 4 : 2 : 2, 4 : 1 : 1, 4 : 2 : 0, 4 : 1 : 0 Y-C
B
-C
R
output
s
Scaled 8-bit luminance only and raw CVBS data output
s
Sliced, decoded VBI data output
2.6 Miscellaneous
s
s
s
s
Power-on control
5 V tolerant digital inputs and I/O ports
Software controlled power saving standby modes supported
Programming via serial I
2
C-bus, full read back ability by an external controller, bit rate
up to 400 kbit/s
s
Boundary scan test circuit complies with the
“IEEE Std. 1149.b1 - 1994”
3. Applications
s
s
s
s
s
Desktop video
Multimedia
Digital television
Image processing
Video phone applications
SAA7114_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
3 of 144
Philips Semiconductors
SAA7114
PAL/NTSC/SECAM video decoder
4. Quick reference data
Table 1:
Symbol
V
DDD
V
DDA
T
amb
P
tot(A+D)
[1]
Quick reference data
Parameter
digital supply voltage
analog supply voltage
ambient temperature
total power dissipation
analog and digital part
CVBS mode
[1]
Conditions
Min
3.0
3.1
0
-
Typ
3.3
3.3
-
0.45
Max
3.6
3.5
70
-
Unit
V
V
°C
W
8-bit image port output mode, expansion port is 3-stated.
5. Ordering information
Table 2:
Type
number
SAA7114E
SAA7114H
Ordering information
Package
Name
LBGA156
LQFP100
Description
plastic low profile ball grid array package; 156 balls;
body 15
×
15
×
1.05 mm
plastic low profile quad flat package; 100 leads;
body 14
×
14
×
1.4 mm
Version
SOT700-1
SOT407-1
SAA7114_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2006
4 of 144
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Product data sheet
Rev. 03 — 17 January 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
SAA7114_3
6. Block diagram
Philips Semiconductors
LLC2
LLC
RTS0
(1)
XCLK
XPD [7:0]
XRH
XRV
XTRI
HPD [7:0]
SDA
SCL
TEST5
TEST3
TEST1
TEST0
RTCO
RTS1
XDQ
XRDY
TEST4
TEST2
REAL-TIME OUTPUT
RES
CE
XTOUT
XTALI
XTALO
AI11
AI12
AI21
AI22
AI23
AI24
AOUT
AI1D
AI2D
AGND
BOUNDARY
SCAN
TEST
ANALOG
DUAL
ADC
CLOCK GENERATION
AND
POWER-ON CONTROL
EXPANSION PORT PIN MAPPING
I/O CONTROL
I
2
C-BUS
X-PORT I/O FORMATTING
chrominance of 16-bit input
SAA7114
PROGRAMMING
REGISTER
ARRAY
A/B
REGISTER
MUX
IPD [7:0]
IDQ
IGPH
EVENT CONTROLLER
IMAGE PORT PIN MAPPING
DIGITAL
DECODER
WITH
ADAPTIVE
COMB
FILTER
IGPV
IGP0
IGP1
FIR-PREFILTER
HORIZONTAL
LINE
VERTICAL
PRESCALER
FINE
FIFO
SCALING
AND
(PHASE)
BUFFER
SCALER BCS
SCALING
VIDEO
FIFO
AUDIO
CLOCK
GENERATION
GENERAL PURPOSE
VBI-DATA SLICER
TEXT
FIFO
32
to
8(16)
MUX
ICLK
ITRDY
VIDEO/TEXT
ARBITER
ITRI
PAL/NTSC/SECAM video decoder
mhc611
TCK
TRST
TDI
AMCLK
TMS
TDO
ASCLK VDD(XTAL) VDDD(ICO1)
to
ALRCLK AMXCLK
VDDD(ICO6)
(1)
VDDA0
to
VDDA2
VSSD(EP1)
to
VSSD(EP4)
VSSD(ICO1)
to
VSSD(ICO3)
VSSA0
to
VSSA2
VSS(XTAL)
VDDD(EP1)
to
VDDD(EP4)
SAA7114
5 of 144
(1) The pins RTCO and ALRCLK are used for configuration of the I
2
C-bus interface and the definition of the crystal oscillator frequency at RESET (pin strapping).
Fig 1. Block diagram
NXP MCU
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