DATASHEET
2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX
Description
The ICS557-06 is a two to four differential clock mux
designed for use in PCI-Express applications. The device
selects one of the two differential HCSL input pairs and fans
out to four pairs of differential HCSL or LVDS outputs.
ICS557-06
Features
•
•
•
•
•
•
•
•
•
Packaged in 20-pin TSSOP
Pb (lead) free packaging
Operating voltage of 3.3 V
Low power consumption
Input differential clock of up to 200 MHz
Jitter 60 ps (cycle-to-cycle)
Output-to-output skew of 50 ps
Available in industrial temperature range (-40 to +85°C)
For PCIe Gen2/3 applications, see the 5V41067A
Block Diagram
VDD
2
OE
CLKA
CLKA
IN1
IN1
IN2
IN2
MUX
2 to 1
CLKB
CLKB
CLKC
CLKC
CLKD
CLKD
2
SEL
GND
PD
Rr (IREF)
IDT®
2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX
1
ICS557-06
REV M 070512
ICS557-06
2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX
PCIE FAN OUT BUFFER
Pin Assignment
SEL
VDDIN
IN1
IN1
PD
IN2
IN2
OE
GND
IREF
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLKA
CLKA
CLKB
CLKB
GND
VDD
CLKC
CLKC
CLKD
CLKD
Select Table
SEL
0
1
Input Pair
selected
IN2/ IN2
IN1/ IN1
20-pin (173 mil) TSSOP
Pin Descriptions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
Name
SEL
VDDIN
IN1
IN1
PD
IN2
IN2
OE
GND
Rr(IREF)
CLKD
CLKD
CLKC
CLKC
VDDOUT
GND
CLKB
CLKB
CLKA
CLKA
Pin
Type
Input
Power
Input
Input
Input
Input
Input
Input
Power
Output
Output
Output
Output
Output
Power
Power
Output
Output
Output
Output
Pin Description
SEL=1 selects IN1/IN1. SEL =0 selects IN2/ IN2. Internal pull-up resistor.
Connect to +3.3 V. Supply voltage for Input clocks.
HCSL true input signal 1.
HCSL complimentary input signal 1.
Powers down the chip and tri-states outputs when low. Internal pull-up
HCSL true input signal 2.
HCSL complimentary input signal 2.
Provides fast output on, tri-states output (High = enable outputs; Low =
disable). Internal pull-up resistor outputs.
Connect to ground.
Precision resistor attached to this pin is connected to the internal current
Differential Complimentary output clock D.
Differential True output clock D.
Differential Complimentary output clock C.
Differential True output clock C.
Connect to +3.3 V. Supply Voltage for Output Clocks.
Connect to ground.
Differential Complimentary output clock B.
Differential True output clock B.
Differential Complimentary output clock A.
Differential True output clock A.
IDT®
2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX
2
ICS557-06
REV M 070512
ICS557-06
2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX
PCIE FAN OUT BUFFER
Application Information
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS557-06 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
External Components
A minimum number of external components are required for
proper operation. Decoupling capacitors of 0.01
μF
should
be connected between VDD and GND pairs (2,9 and 15,16)
as close to the device as possible.
Current Reference Source R
r
(Iref)
If board target trace impedance (Z) is 50Ω then Rr = 475Ω
,
(1%), providing IREF of 2.32 mA, output current (I
OH
) is
equal to 6*IREF.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the ICS557-06.
This includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the device.
Load Resistors R
L
Since the clock outputs are open source outputs, 50 ohm
external resistors to ground are to be connected at each
clock output.
Output Termination
The PCI-Express differential clock outputs of the ICS557-06
are open source drivers and require an external series
resistor and a resistor to ground. These resistor values and
their allowable locations are shown in detail in the
PCI-Express Layout Guidelines
section.
The ICS557-06 can also be configured for LVDS compatible
voltage levels. See the
LVDS Compatible Layout
Guidelines
section.
IDT®
2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX
3
ICS557-06
REV M 070512
ICS557-06
2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX
PCIE FAN OUT BUFFER
Output Structures
IREF
=2.3 mA
6*IREF
R
R
475
Ω
See Output Termination
Sections - Pages 3 ~ 5
General PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
2. No vias should be used between decoupling capacitor
and VDD pin.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the ICS557-06.This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
IDT®
2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX
4
ICS557-06
REV M 070512
ICS557-06
2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX
PCIE FAN OUT BUFFER
PCI-Express Layout Guidelines
Common Recommendations for Differential Routing
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
L3 length, Route as non-coupled 50 ohm trace.
R
S
R
T
Differential Routing on a Single PCB
L4 length, Route as coupled
microstrip
100 ohm differential trace.
L4 length, Route as coupled
stripline
100 ohm differential trace.
Differential Routing to a PCI Express Connector
L4 length, Route as coupled
microstrip
100 ohm differential trace.
L4 length, Route as coupled
stripline
100 ohm differential trace.
Dimension or Value
0.5 max
0.2 max
0.2 max
33
49.9
Dimension or Value
2 min to 16 max
1.8 min to 14.4 max
Dimension or Value
0.25 to 14 max
0.225 min to 12.6 max
Unit
inch
inch
inch
ohm
ohm
Unit
inch
inch
Unit
inch
inch
PCI-Express Device Routing
L1
R
S
L1’
R
S
L2
L4
L4’
R
T
L3’
R
T
L3
L2’
ICS557-06
Output
Clock
PCI-Express
Load or
Connector
Typical PCI-Express (HCSL) Waveform
700 mV
0
t
OR
0.52 V
0.175 V
500 ps
500 ps
t
OF
0.52 V
0.175 V
IDT®
2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX
5
ICS557-06
REV M 070512
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
