CAT310
10 Channel Automotive LED
Display Driver
Description
The CAT310 is a 10−channel LED driver for automotive and other
lighting applications. All LED output channels are driven from a low
on−resistance open−drain High Voltage CMOS Nch−FETs and are
fully compliant with “Load Dump” transients of up to 40 volts. The
LED bias current of each channel can be set independently using an
external series ballast resistor, making the device ideal for multi−color
instrumentation displays.
A high−speed serial interface (suitable with both 3.3 volt and 5 volt
systems) feeding a 10 bit shift register is used to program the desired
state (on/off) of each channel. The device offers a blanking control pin
(BLANK) which can be used to disable all channels on demand. A
serial output data pin (SOUT) is provided to daisy−chain devices in
large cluster LED applications.
During initial power up all channels are reset and cleared via an
under−voltage lock out (UVLO) detector and for added protection all
channels are disabled in the event of a battery over−voltage condition
(19 volts or more).
Features
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SOIC−20
W SUFFIX
CASE 751BJ
PIN CONNECTIONS
SCLK
XLAT
SIN
SOUT
GND
OUT4
OUT3
OUT2
OUT1
OUT0
1
NC
BLANK
VCC
VBATT
PGND
OUT5
OUT6
OUT7
OUT8
OUT9
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•
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•
•
•
•
•
•
•
Automotive “Load Dump” Protection (40 V)
10 Independent LED Channels
Up to 50 mA Output per Channel
Overvoltage Detection at 19 V
Serial Interface for Channel Programming
Daisy Chain Output for Multi−driver Cascading
LED Blanking Control
Operating Temperature from
−40°C
to +125°C
20−pin SOIC Package
This Device is Pb−Free, Halogen Free/BFR Free and RoHS
Compliant
Automotive Lighting
White and Other Color High Brightness LEDs
Multi−color High−brightness LED Cluster Displays
General LED Lighting
MARKING DIAGRAM
CAT310W
CAT310W = Specific Device Code
Applications
•
•
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ORDERING INFORMATION
Device
CAT310W
Package
SOIC−20
(Pb−Free)
Shipping
1,000/Tape & Reel
©
Semiconductor Components Industries, LLC, 2009
November, 2009
−
Rev. 2
1
Publication Order Number:
CAT310/D
CAT310
V
BATTERY
14 V (typical)
RS1
RS2
OUT1
RS10
330
W
OUT9
30 mA
VBATT OUT0
V
CC
5V
1
mF
VCC
BLANK
CAT310
XLAT
SIN
SCLK GND PGND
SOUT
Figure 1. Typical Application Circuit
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
VCC voltage
Input voltage range (SIN, SCLK, BLANK, XLAT)
SOUT voltage range
Peak OUT0 to OUT9 voltage
VBATT input voltage
DC output current on OUT0 to OUT9
Storage Temperature Range
Operating Junction Temperature Range
Lead Soldering Temperature (10 sec.)
ESD Rating: Low Voltage Pins
Human Body Model
Machine Model
ESD Rating: VBATT, OUT[0:9] pins
Human Body Model
Machine Model
Rating
7
−0.3
V to VCC + 0.3 V
−0.3
V to VCC + 0.3 V
40
40
70
−55
to +160
−40
to +150
300
3000
300
V
1000
100
Unit
V
V
V
V
V
mA
°C
°C
°C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 2. RECOMMENDED OPERATING CONDITIONS
Parameter
VCC
Voltage applied to OUT0 to OUT9
Output current on OUT0 to OUT9
Ambient Temperature Range
Range
3.0 to 5.5
9 to 17
0 to 50
−40
to +125
Unit
V
V
mA
_C
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CAT310
Electrical Operating Characteristics
Table 3. DC CHARACTERISTICS
(VCC = 5.0 V,
−40°C
≤
T
A
≤
125°C, over recommended operating conditions unless specified otherwise.)
Symbol
I
STBY
V
OVP
V
UVLO
R
SW
I
O(n)LKG
I
XLAT
I
BLANK
V
IH
V
IL
I
IL
V
OH
V
OL
Name
Standby Quiescent Current
VBATT Over Voltage
Protection Trigger threshold
VCC Under Voltage Lockout
Trigger threshold
Switch on resistance for OUT0 to OUT9
OUT0 to OUT9 Output Switch Leakage
XLAT Internal Pull−down current
BLANK Internal Pull−up current
Logic high input voltage
Logic low input voltage
Logic Input leakage current
(SCLK, SIN)
SOUT logic high output voltage
SOUT logic low output voltage
V
I
= V
CC
or GND
I
OH
=
−1
mA
I
OL
= 1 mA
I
O(n)
= 30 mA
V
(OUT(n))
= 15 V
XLAT = V
CC
XLAT = 0.3 V
BLANK = 0 V
BLANK = V
CC
−
0.3 V
4
1
4
1
0.3 V
CC
−5
V
CC
−0.3
V
0.3
0
5
mA
V
2
Conditions
Static input signal.
All outputs turned off.
17
Min
Typ
1
19
1.7
5
0.1
10
3
10
3
Max
10
21
2.5
12
10
30
6
30
6
0.7 V
CC
Units
mA
V
V
W
mA
mA
mA
V
Table 4. SWITCHING CHARACTERISTICS
(VCC = 5.0 V,
−40°C
≤
T
A
≤
125°C, over recommended operating conditions unless specified otherwise.)
Symbol
SCLK
f
SCLK
t
wh/wl
SIN
t
su
t
h
XLAT
t
w
t
h
t
r
t
f
t
pd
t
pd
t
pd
XLAT Pulse width
Hold time
SCLK to XLAT
SOUT rise time (10% to 90%)
SOUT fall time (90% to 10%)
Propagation delay time
Propagation delay time
Propagation delay time
C
L
= 15 pF
C
L
= 15 pF
Blank
↑
to OUT(n)
Blank
↓
to OUT(n)
SCLK to SOUT
SIN to SCLK
20
20
20
15
25
25
25
ns
ns
ns
ns
ns
ns
ns
Setup time SIN to SCLK
Hold time SIN to SCLK
10
10
ns
ns
SCLK Clock Frequency
SCLK Pulse width
High or Low
30
10
MHz
ns
Name
Conditions
Min
Typ
Max
Units
1. All logic inputs contain Schmitt trigger inputs.
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CAT310
2.5 V UVLO
+
VCC
–
RESET
SCLK
SIN
10 BIT SHIFT
REGISTER
SOUT
XLAT
10 BIT
DATA LATCHES
OUT0
BLANK
VBATT
+
–
19 V
GND
PGND
OR
DISABLE
10 BIT DRIVER
DRV9
SW−0
SW−9
OUT9
DRV0
Figure 2. Block Diagram
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CAT310
PIN DESCRIPTIONS
VCC
is the supply input for the internal logic and is
compatible with both 3.3 V and 5 V systems. The logic is
held in a reset state until VCC exceeds 2.5 V. It is
recommended that a small bypass ceramic capacitor (1
mF)
be placed between VCC and GND pins on the device.
SIN
is the CMOS logic pin for delivering the serial input
data stream into the internal 10−bit shift register. The most
recent or last data value in the serial stream is used to
configure the state of output channel “zero” (OUT0). During
the initial power up sequence all contents of the shift register
are reset and cleared to zero.
SCLK
is the CMOS logic pin used to clock the internal shift
register. On each rising edge of clock, the serial data will
advance through one stage of the shift register.
XLAT
is the CMOS logic input used to transfer data from
the 10−bit shift register into the output channel latches. An
internal pull−down current of 10 microampere is present on
this pin. When XLAT is low, the state of each output channel
remains unchanged. When XLAT is driven high, the
contents of the shift register appear at their respective output
channels. An external pull−up resistance of 10 kW or less is
adequate for logic high.
PGND, GND
pins should be connected to the ground on the
PCB.
BLANK
is the CMOS logic input (active high) used to
temporarily disable all outputs. An internal pull−up current
of 10 microampere is present on this pin. The BLANK pin
must be driven to a logic low in order for channel outputs to
resume normal operation. An external pull−down resistance
of 10 kW or less is adequate for logic low.
SOUT
is the CMOS logic output used for daisy chain
applications. The serial output data stream is fed from the
last stage of the internal 10−bit shift register. On each rising
edge of the clock, the SOUT value will be updated. The data
value present on this pin is identical to the data value being
used for configuring the state of output channel nine
(OUT9). At initial power up, the SOUT data stream will
contain all zeroes until the shift register has been fully
loaded.
VBATT
input monitors the battery voltage. If an
over−voltage, above 19 V typical, is detected, all outputs are
disabled. Upon conclusion of the over−voltage condition, all
outputs resume normal operation. The current drawn by the
VBATT pin is less than 1 microampere during normal
operation.
OUT0−OUT9
are the ten LED outputs connected internally
to the switch N−channel FETs. They sink currents up to
50 mA per channel and can withstand transients up to 40 V
compatible with automotive “load dump”. The output
on−resistance is 5
W,
and the off−resistance is 5 MW.
Table 5. PIN TABLE
Pin Number
1
2
3
4
5
6−10
11−15
16
17
18
19
20
Pin Name
SCLK
XLAT
SIN
SOUT
GND
OUT4
−
OUT0
OUT9
−
OUT5
PGND
VBATT
VCC
BLANK
N.C.
Description/Function
Clock input for the data shift register.
Control input for the data latch.
Serial data input.
Serial data output.
Ground.
Open drain outputs.
Open drain outputs.
Ground for LED driver outputs.
Battery sense input.
Power supply voltage for the logic
Blank input. When BLANK is high, all the output drivers are turned off.
No connect.
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PCB设计
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