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74ALVT162823DL512: 产品描述Flip Flops 18-BIT BUS 35 W/30; 产品类别半导体逻辑; 文件大小105KB，共21页; 制造商NXP(恩智浦); 官网地址https://www.nxp.com

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74ALVT162823DL512概述

Flip Flops 18-BIT BUS 35 W/30

74ALVT162823DL512规格参数

参数名称	属性值
Product Attribute	Attribute Value
制造商 Manufacturer	NXP(恩智浦)
产品种类 Product Category	Flip Flops
RoHS	Details
Number of Circuits	2
Logic Family	ALVT
Logic Type	D-Type Edge Triggered Flip-Flop
Polarity	Non-Inverting
Input Type	Single-Ended
传播延迟时间 Propagation Delay Time	3 ns at 3.3 V
High Level Output Current	- 12 mA
电源电压-最大 Supply Voltage - Max	3.6 V
最小工作温度 Minimum Operating Temperature	- 40 C
最大工作温度 Maximum Operating Temperature	+ 85 C
安装风格 Mounting Style	SMD/SMT
封装 / 箱体 Package / Case	SOT-371
系列 Packaging	Tube
高度 Height	2.35 mm
长度 Length	18.55 mm
Quiescent Current	3.9 mA
宽度 Width	7.6 mm
Number of Input Lines	9
Number of Output Lines	9
工作电源电压 Operating Supply Voltage	2.5 V, 3.3 V
Reset Type	Master Reset
工厂包装数量 Factory Pack Quantity	1326
电源电压-最小 Supply Voltage - Min	2.3 V

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74ALVT162823

18-bit bus-interface D-type ﬂip-ﬂop with reset and enable with

Ω

termination resistors; 3-state

Rev. 02 — 11 August 2005

Product data sheet

1. General description

The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra

packages required to buffer existing registers and provide extra data width for wider data

or address paths of buses carrying parity.

The 74ALVT162823 has two 9-bit wide buffered registers with clock enable (nCE) and

master reset (nMR) which are ideal for parity bus interfacing in high microprogrammed

systems.

The registers are fully edge-triggered. The state of each D input, one set-up time before

the LOW-to-HIGH clock transition is transferred to the corresponding Q output of the

ﬂip-ﬂop.

The 74ALVT162823 is designed with 30

Ω

series resistance in both the pull-up and

pull-down output structures. This design reduces line noise in applications such as

memory address drivers, clock drivers, and bus receivers or transmitters.

2. Features

Two sets of high speed parallel registers with positive edge-triggered D-type ﬂip-ﬂops

5 V I/O compatible

Ideal where high speed, light loading or increased fan-in are required with MOS

microprocessors

Bus hold data inputs eliminate the need for external pull-up resistors to hold unused

inputs

Live insertion and extraction permitted

Power-up 3-state

Power-up reset

Output capability: +12 mA to

−12

Outputs include series resistance of 30

Ω

making external termination resistors

unnecessary

Latch-up protection:

JESD78: exceeds 500 mA

ESD protection:

MIL STD 883, method 3015: exceeds 2000 V

Machine Model: exceeds 200 V

74ALVT162823DL512相似产品对比

	74ALVT162823DL512	74ALVT162823DGGY	74ALVT162823DGG11
描述	Flip Flops 18-BIT BUS 35 W/30	Flip Flops 18-Bit Bus-Interface D-Type Flip-Flop	Flip Flops 18-BIT BUS 35 W/30
Product Attribute	Attribute Value	-	Attribute Value
制造商 Manufacturer	NXP(恩智浦)	-	NXP(恩智浦)
产品种类 Product Category	Flip Flops	-	Flip Flops
RoHS	Details	-	Details
Number of Circuits	2	-	2
Logic Family	ALVT	-	ALVT
Logic Type	D-Type Edge Triggered Flip-Flop	-	D-Type Edge Triggered Flip-Flop
Polarity	Non-Inverting	-	Non-Inverting
Input Type	Single-Ended	-	Single-Ended
传播延迟时间 Propagation Delay Time	3 ns at 3.3 V	-	3 ns at 3.3 V
High Level Output Current	- 12 mA	-	- 12 mA
电源电压-最大 Supply Voltage - Max	3.6 V	-	3.6 V
最小工作温度 Minimum Operating Temperature	- 40 C	-	- 40 C
最大工作温度 Maximum Operating Temperature	+ 85 C	-	+ 85 C
安装风格 Mounting Style	SMD/SMT	-	SMD/SMT
封装 / 箱体 Package / Case	SOT-371	-	SOT-364
系列 Packaging	Tube	-	Tube
高度 Height	2.35 mm	-	1.05 mm
长度 Length	18.55 mm	-	14.1 mm
Quiescent Current	3.9 mA	-	3.9 mA
宽度 Width	7.6 mm	-	6.2 mm
Number of Input Lines	9	-	9
Number of Output Lines	9	-	9
工作电源电压 Operating Supply Voltage	2.5 V, 3.3 V	-	2.5 V, 3.3 V
Reset Type	Master Reset	-	Master Reset
工厂包装数量 Factory Pack Quantity	1326	-	875
电源电压-最小 Supply Voltage - Min	2.3 V	-	2.3 V

74ALVT162823DL512

74ALVT162823DL512在线购买

74ALVT162823DL512概述

74ALVT162823DL512规格参数

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74ALVT162823DL512相似产品对比

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