The SUM60N04-12LT is a 40 V N-Channel, 15 mΩ logic
level MOSFET in a 5-lead D
2
PAK package built on the
Vishay Siliconix proprietary high-cell density TrenchFET
technology.
Two anti-parallel electrically isolated poly-silicon diodes are
used to sense the temperature changes in the MOSFET.
The gate of the MOSFET is protected from high voltage
transients by two back-to-back poly-silicon zener diodes.
APPLICATIONS
• Industrial
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
D
2
Pak
TO-263, 5 Leads
D
T
1
1 2 3 4 5
G
T
2
D
1
D
2
G T
1
D T
2
S
S
Ordering Information:
SUM60N04-12LT
SUM60N04-12LT-E3 (Lead (Pb)-free)
N-Channel MOSFET
* Pb containing terminations are not RoHS compliant, exemptions may apply.
Document Number: 71620
S-80272-Rev. C, 11-Feb-08
www.vishay.com
1
SUM60N04-12LT
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
T
A
= 25 °C, unless otherwise noted
Parameter
Drain-Source Voltage
Gate-Source Voltage
V
GS
Clamp Current
Continuous Drain Current (T
J
= 175 °C)
Avalanche Current
Repetitive Avalanche Energy
Source-to-Anode Voltage
Source-to-Cathode Voltage
Maximum Power Dissipation
a
Operating Junction and Storage Temperature Range
T
C
= 25 °C
T
A
= 25 °C
d
L = 0.1 mH
T
C
= 25 °C
T
C
= 100 °C
Symbol
V
DS
V
GS
I
G
I
D
I
AR
E
AR
V
SA
V
SC
P
D
T
J
, T
stg
Limit
40
± 20
50
60
a
50
50
125
100
100
110
3.75
- 55 to 175
W
°C
mJ
V
A
Unit
V
mA
THERMAL RESISTANCE RATINGS
Parameter
Junction-to-Ambient
Junction-to-Case
Notes:
a. Package limited.
b. Duty Cycle
≤
1 %.
c. See SOA curve for voltage derating.
d. When Mounted on 1" square PCB FR4.
d
Symbol
R
thJA
R
thJC
Limit
40
1.35
Unit
°C/W
www.vishay.com
2
Document Number: 71620
S-80272-Rev. C, 11-Feb-08
SUM60N04-12LT
Vishay Siliconix
MOSFET SPECIFICATIONS
T
J
= 25 °C, unless otherwise noted
Parameter
Static
Drain-Source Breakdown Voltage
V
GS
Clamp Voltage
Gate-Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
V
(BR)DSS
V
GS
V
GS(th)
I
GSS
I
DSS
V
GS
= 0 V, I
D
= 1 mA
V
DS
= 0 V, I
G
= 20 µA
V
DS
= V
GS
, I
DS
= 1 mA
V
DS
= 0 V, V
GS
= ± 5 V
V
DS
= 40 V, V
GS
= 0 V
V
DS
= 40 V, V
GS
= 0 V, T
J
= 125 °C
V
DS
= 40 V, V
GS
= 0 V, T
J
= 175 °C
V
GS
= 10 V, I
D
= 20 A
Drain-Source On-State Resistance
a
r
DS(on)
V
GS
= 10 V, I
D
= 20 A, T
J
= 125 °C
V
GS
= 10 V, I
D
= 20 A, T
J
= 175 °C
V
GS
= 4.5 V, I
D
= 20 A
Sense Diode Forward Voltage
Sense Diode Forward Voltage Increase
Forward
Transconductance
a
Dynamic
b
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
c
Gate-Source Charge
c
Gate-Drain Charge
Gate Resistance
Turn-On Delay Time
c
Rise Time
Fall Time
c
Continuous Current
Pulsed Current
Forward Voltage
a
Reverse Recovery Time
c
c
Symbol
Test Conditions
Min.
40
10
1
Typ.
Max.
Unit
20
2
± 250
1
50
250
0.0075
0.009
0.0135
0.018
0.0095
0.012
735
735
50
35
V
nA
µA
Ω
V
FD1
V
FD2
ΔV
F
g
fs
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
R
g
t
d(on)
t
r
t
d(off)
t
f
b
I
F
= 250 µA
I
F
= 250 µA
From I
F
= 125 µA to I
F
= 250 µA
V
DS
= 15 V, I
D
= 20 A
675
675
25
mV
S
1920
V
GS
= 0 V, V
DS
= 25 V, f = 1 MHz
560
210
51
V
DS
= 20 V, V
GS
= 10 V, I
D
= 25 A
1.2
20
V
DD
= 20 V, R
L
= 0.8
Ω
I
D
≅
25 A, V
GEN
= 10 V, R
g
= 2.5
Ω
70
35
20
5.5
12
4.1
40
120
70
40
60
240
I
F
= 60 A, V
GS
= 0 V
I
F
= 60 A, di/dt = 100 A/µs
40
1.4
60
ns
Ω
70
nC
pF
Turn-Off Delay Time
c
Source-Drain Diode Ratings and Characteristics
T
C
= 25 °C
I
S
I
SM
V
SD
t
rr
A
V
ns
Notes:
a. Pulse test; pulse width
≤
300 µs, duty cycle
≤
2 %.
b. Guaranteed by design, not subject to production testing.
c. Independent of operating temperature.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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