NCP5304
High Voltage, High and Low
Side Driver
The NCP5304 is a High Voltage Power gate Driver providing two
outputs for direct drive of 2 N−channel power MOSFETs or IGBTs
arranged in a half−bridge configuration.
It uses the bootstrap technique to insure a proper drive of the
High−side power switch. The driver works with 2 independent inputs
with cross conduction protection.
Features
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MARKING
DIAGRAMS
1
SOIC−8
D SUFFIX
CASE 751
8
P5304
ALYW
G
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High Voltage Range: up to 600 V
dV/dt Immunity
±50
V/nsec
Negative Current Injection Characterized Over the Temperature Range
Gate Drive Supply Range from 10 V to 20 V
High and Low Drive Outputs
Output Source / Sink Current Capability 250 mA / 500 mA
3.3 V and 5 V Input Logic Compatible
Up to V
CC
Swing on Input Pins
Extended Allowable Negative Bridge Pin Voltage Swing to −10 V
for Signal Propagation
Matched Propagation Delays between Both Channels
Outputs in Phase with the Inputs
Cross Conduction Protection with 100 ns Internal Fixed Dead Time
Under V
CC
LockOut (UVLO) for Both Channels
Pin−to−Pin Compatible with Industry Standards
These are Pb−Free Devices
1
PDIP−8
P SUFFIX
CASE 626
NCP5304
A
L or WL
Y or YY
W or WW
G or
G
NCP5304
AWL
YYWWG
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Typical Applications
•
Half−bridge Power Converters
•
Full−bridge Converters
PINOUT INFORMATION
IN_LO
IN_HI
VCC
GND
1
2
3
4
8
7
6
5
VBOOT
DRV_HI
BRIDGE
DRV_LO
8 Pin Package
ORDERING INFORMATION
Device
NCP5304PG
NCP5304DR2G
Package
PDIP−8
(Pb−Free)
Shipping
†
50 Units / Rail
SOIC−8 2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2014
1
November, 2014 − Rev. 7
Publication Order Number:
NCP5304/D
NCP5304
Vbulk
+
C1
D4
Q1
C3
GND
U1
8
IN_LO VBOOT
2
7
IN_HI DRV_HI
3
6
Vcc
Bridge
4
5
GND DRV_LO
1
NCP5304
GND
GND
D3
GND
U2
R1
C4
Lf
Out−
D2
Q2
C6
T1
D1
L1
+
C3
Out+
GND
Vcc
NCP1395
GND
Figure 1. Typical Application Resonant Converter (LLC type)
+
Vbulk
C1
D4
Q1
C3
GND
U1
1
8
IN_LO VBOOT
2
7
IN_HI DRV_HI
3
6
Vcc
Bridge
4
5
GND DRV_LO
NCP5304
GND
GND
D3
GND
U2
R1
C4
T1
D1
C5
L1
+
C3
Out−
D2
Q2
C6
Out+
GND
Vcc
NCP1395
GND
Figure 2. Typical Application Half Bridge Converter
VCC
VCC
IN_HI
UV
DETECT
PULSE
TRIGGER
LEVEL
SHIFTER
S Q
R Q
UV
DETECT
VBOOT
DRV_HI
BRIDGE
VCC
GND
CROSS
CONDUCTION
PREVENTION
GND
IN_LO
DELAY
DRV_LO
GND
GND
GND
Figure 3. Detailed Block Diagram
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2
NCP5304
PIN DESCRIPTIONS
Pin No.
1
2
3
4
5
6
7
8
Pin Name
IN_LO
IN_HI
VCC
GND
DRV_LO
BRIDGE
DRV_HI
VBOOT
Logic Input for Low side driver output in phase
Logic Input for High side driver output in phase
Low side and main power supply
Ground
Low side gate drive output
Bootstrap return or High side floating supply return
High side gate drive output
Bootstrap power supply
Pin Function
MAXIMUM RATINGS
Rating
V
CC
V
CC_transient
V
BRIDGE
V
BRIDGE
V
BOOT−
V
BRIDGE
V
DRV_HI
V
DRV_LO
dV
BRIDGE
/dt
V
IN_XX
Main power supply voltage
Main transient power supply voltage:
IV
CC_max
= 5 mA during 10 ms
VHV: High Voltage BRIDGE pin
Allowable Negative Bridge Pin Voltage for IN_LO Signal Propagation to DRV_LO
(see characterization curves for detailed results)
VHV: Floating supply voltage
VHV: High side output voltage
Low side output voltage
Allowable output slew rate
Inputs IN_HI, IN_LO
ESD Capability:
− HBM model (all pins except pins 6−7−8 in 8 pins
package or 11−12−13 in 14 pins package)
− Machine model (all pins except pins 6−7−8 in 8 pins
package or 11−12−13 in 14 pins package)
Latch up capability per Jedec JESD78
R
qJA
Power dissipation and Thermal characteristics
PDIP−8: Thermal Resistance, Junction−to−Air
SO−8: Thermal Resistance, Junction−to−Air
Maximum Operating Junction Temperature
°C/W
100
178
+150
°C
Symbol
Value
−0.3 to 20
23
−1 to 600
−10
−0.3 to 20
V
BRIDGE
− 0.3 to
V
BOOT
+ 0.3
−0.3 to V
CC
+ 0.3
50
−1.0 to V
CC
+ 0.3
2
200
Unit
V
V
V
V
V
V
V
V/ns
V
kV
V
T
J_max
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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3
NCP5304
ELECTRICAL CHARACTERISTIC
(V
CC
= V
boot
= 15 V, V
GND
= V
bridge
, −40°C < T
J
< 125°C, Outputs loaded with 1 nF)
T
J
−40°C to 125°C
Rating
OUTPUT SECTION
Output high short circuit pulsed current V
DRV
= 0 V, PW
v
10
ms
(Note 1)
Output low short circuit pulsed current V
DRV
= V
CC
, PW
v
10
ms
(Note 1)
Output resistor (Typical value @ 25°C) Source
Output resistor (Typical value @ 25°C) Sink
High level output voltage, V
BIAS
−V
DRV_XX
@ I
DRV_XX
= 20 mA
Low level output voltage V
DRV_XX
@ I
DRV_XX
= 20 mA
DYNAMIC OUTPUT SECTION
Turn−on propagation delay (Vbridge = 0 V)
Turn−off propagation delay (Vbridge = 0 V or 50 V) (Note 2)
Output voltage rise time (from 10% to 90% @ V
CC
= 15 V) with 1 nF load
Output voltage fall time (from 90% to 10% @V
CC
= 15 V) with 1 nF load
Propagation delay matching between the High side and the Low side
@ 25°C (Note 3)
Internal fixed dead time (Note 4)
Minimum input width that changes the output
Maximum input width that does not change the output
INPUT SECTION
Low level input voltage threshold
Input pull−down resistor (V
IN
< 0.5 V)
High level input voltage threshold
Logic “1” input bias current @ V
IN_XX
= 5 V @ 25°C
Logic “0” input bias current @ V
IN_XX
= 0 V @ 25°C
SUPPLY SECTION
V
CC
UV Start−up voltage threshold
V
CC
UV Shut−down voltage threshold
Hysteresis on V
CC
Vboot Start−up voltage threshold reference to bridge pin
(Vboot_stup = Vboot − Vbridge)
Vboot UV Shut−down voltage threshold
Hysteresis on Vboot
Leakage current on high voltage pins to GND
(V
BOOT
= V
BRIDGE
= DRV_HI = 600 V)
Consumption in active mode (V
CC
= Vboot, fsw = 100 kHz and 1 nF load on
both driver outputs)
Consumption in inhibition mode (V
CC
= Vboot)
V
CC
current consumption in inhibition mode
Vboot current consumption in inhibition mode
VCC_stup
VCC_shtdwn
VCC_hyst
Vboot_stup
Vboot_shtdwn
Vboot_shtdwn
I
HV_LEAK
ICC1
ICC2
ICC3
ICC4
8.0
7.3
0.3
8.0
7.3
0.3
−
−
−
−
−
8.9
8.2
0.7
8.9
8.2
0.7
5
4
250
200
50
9.9
9.1
−
9.9
9.1
−
40
5
400
−
−
V
V
V
V
V
V
mA
mA
mA
mA
mA
V
IN
R
IN
V
IN
I
IN+
I
IN−
−
−
2.3
−
−
−
200
−
5
−
0.8
−
−
25
2.0
V
kW
V
mA
mA
t
ON
t
OFF
tr
tf
Dt
DT
t
PW1
t
PW2
−
−
−
−
−
65
−
20
100
100
85
35
20
100
−
−
170
170
160
75
35
190
50
−
ns
ns
ns
ns
ns
ns
ns
ns
I
DRVsource
I
DRVsink
R
OH
R
OL
V
DRV_H
V
DRV_L
−
−
−
−
−
−
250
500
30
10
0.7
0.2
−
−
60
20
1.6
0.6
mA
mA
W
W
V
V
Symbol
Min
Typ
Max
Units
1. Parameter guaranteed by design
2. Turn−off propagation delay @ Vbridge = 600 V is guaranteed by design
3. See characterization curve for
Dt
parameters variation on the full range temperature.
4. Timing diagram definition see Figure 7.
5. Timing diagram definition see Figure 5 and Figure 6.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NCP5304
IN_HI
IN_LO
DRV_HI
DRV_LO
Figure 4. Input/Output Timing Diagram
IN_HI
(IN_LO)
t
on
50%
t
r
50%
t
f
t
off
90%
90%
DRV_HI
(DRV_LO)
10%
10%
Figure 5. Propagation Delay and Rise / Fall Time Definition
IN_HI
50%
50%
toff_HI
ton_HI
90%
DRV_HI
10%
Matching Delay1=ton_HI−ton_LO
Matching Delay2=toff_HI−toff_LO
IN_LO
50%
50%
toff_LO
90%
DRV_LO
ton_LO
10%
Figure 6. Matching Propagation Delay
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