CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
Electrical Specifications
PARAMETER
SUPPLY
V
IN
V
LOR
V
LOF
I
S
I
SS
T
FD
V
REF
V
IN
= 3V, V
BOOST
= V
SUP
= 12V, V
SRC
= 20V, Over-temperature from -40°C to +85°C.
Unless Otherwise Specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
Input Supply Range
Undervoltage Lockout Threshold
Undervoltage Lockout Threshold
Quiescent Current
Quiescent Current - Switching
Fault Delay Time
Reference Voltage
V
IN
rising
V
IN
falling
LX not switching
LX switching
C
DEL
= 100nF
T
A
= +25°C
2.6
2.4
2.2
2.5
2.3
5.5
2.6
2.4
2.5
5
23
10
V
V
V
mA
mA
ms
1.19
1.187
1.215
1.215
140
1.235
1.238
V
V
°C
SHUTDN
Thermal Shutdown Temperature
MAIN BOOST REGULATOR
V
BOOST
f
OSC
D
CM
V
FBB
Output Voltage Range
Oscillator Frequency
Maximum Duty Cycle
Boost Feedback Voltage
T
A
= +25°C
(Note 1)
V
IN
+15%
1050
82
1.192
1.188
V
FTB
V
BOOST
/I
BOOST
V
BOOST
/V
IN
I
FB
gmV
r
ON
LX
I
LEAK
LX
I
LIM
LX
t
SS
B
FB Fault Trip Level
Load Regulation
Line Regulation
Input Bias Current
FB Transconductance
LX ON-resistance
LX Leakage Current
LX Current Limit
Soft-Start Period
V
FB
= 1.35V, V
LX
= 13V
Duty cycle = 65% (Note 1)
C
DEL
= 100nF
2.4
Falling edge
50mA < I
LOAD
< 250mA
V
IN
= 2.6V to 5.5V
V
FB
= 1.35V
dI = ±2.5µA at COMP, FB = COMP
150
160
200
0.02
2.8
7
250
40
3.3
0.85
1200
85
1.205
1.205
0.925
0.1
0.08
500
1.218
1.222
1.020
18
1350
V
kHz
%
V
V
V
%
%/V
nA
µA/V
m
µA
A
ms
3
FN6436.0
June 18, 2007
ISL97642
Electrical Specifications
PARAMETER
OPERATIONAL AMPLIFIERS
V
SUP
I
SUP
V
OS
I
B
CMIR
CMRR
A
OL
V
OH
Supply Operating Range
Supply Current per Amplifier
Offset Voltage
Input Bias Current
Common Mode Input Range
Common Mode Rejection Ratio
Open Loop Gain
Output Voltage High
I
OUT
= 100µA
I
OUT
= 5mA
V
OL
Output Voltage Low
I
OUT
= -100µA
I
OUT
= -5mA
I
SC
I
CONT
PSRR
BW
-3dB
GBWP
SR
POSITIVE LDO
V
FBP
Positive Feedback Voltage
I
DRVP
= 100µA, T
A
= +25°C
I
DRVP
= 100µA
V
FTP
I
BP
V
POS
/I
POS
I
DRVP
I
LEAK
P
t
SS
P
NEGATIVE LDO
V
FBN
FBN Regulation Voltage
I
DRVN
= 0.2mA, T
A
= +25°C
I
DRVN
= 0.2mA
V
FTN
I
BN
V
FBN
Fault Trip Level
Negative LDO Input Bias Current
FBN Load Regulation
I
DRVN
I
LEAK
N
t
SS
N
V
ON
-SLICE CIRCUIT
V
LO
V
HI
CTL Input Low Voltage
CTL Input High Voltage
V
IN
= 2.6V to 5.5V
V
IN
= 2.6V to 5.5V
0.6V
IN
0.4V
IN
V
V
Source Current
DRVN Off Leakage Current
Soft-start Period
V
FBN
rising
V
FBN
= 250mV
V
DRVN
= -6V, I
DRVN
= 2µA to 20µA
V
FBN
= 500mV, V
DRVN
= -6V
V
FBP
= 1.35V, V
DRVP
= 30V
C
DEL
= 100nF
2
0.173
0.171
380
-50
0.5
4
0.1
7
10
0.203
0.203
430
0.233
0.235
480
50
V
V
mV
nA
%
mA
µA
ms
V
FBP
Fault Trip Level
Positive LDO Input Bias Current
FBP Load Regulation
Sink Current
DRVP Off Leakage Current
Soft-Start Period
V
FBP
falling
V
FBP
= 1.4V
V
DRVP
= 25V, I
DRVP
= 0µA to 20µA
V
FBP
= 1.1V, V
DRVP
= 10V
V
FBP
= 1.4V, V
DRVP
= 30V
C
DEL
= 100nF
2
1.176
1.176
0.82
-50
0.5
4
0.1
7
10
1.2
1.2
0.9
1.224
1.229
0.98
50
V
V
V
nA
%
mA
µA
ms
Short-Circuit Current
Continuous Output Current
Power Supply Rejection Ratio
-3dB Bandwidth
Gain Bandwidth Product
Slew Rate
100
±50
60
100
12
8
12
V
SUP
-15
V
SUP
-250
-50
0
60
90
110
V
SUP
-2
V
SUP
-150
2
100
150
30
150
4.5
600
3
18
800
12
+50
V
SUP
V
µA
mV
nA
V
dB
dB
mV
mV
mV
mV
mA
mA
dB
MHz
MHz
V/µs
V
IN
= 3V, V
BOOST
= V
SUP
= 12V, V
SRC
= 20V, Over-temperature from -40°C to +85°C.
Unless Otherwise Specified.
(Continued)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
4
FN6436.0
June 18, 2007
ISL97642
Electrical Specifications
PARAMETER
I
LEAK
CTL
t
D
rise
V
IN
= 3V, V
BOOST
= V
SUP
= 12V, V
SRC
= 20V, Over-temperature from -40°C to +85°C.
Unless Otherwise Specified.
(Continued)
DESCRIPTION
CTL Input Leakage Current
CTL to OUT Rising Prop Delay
CONDITIONS
CTL = AGND or IN
1k from DRN to 8V, V
CTL
= 0V to
3V step, no load on OUT, measured
from V
CTL
= 1.5V to OUT = 20%
1k from DRN to 8V, V
CTL
= 3V to
0V step, no load on OUT, measured
from V
CTL
= 1.5V to OUT = 80%
MIN
-1
100
TYP
MAX
1
UNIT
µA
ns
t
D
fall
CTL to OUT Falling Prop Delay
100
ns
V
SRC
ISRC
SRC Input Voltage Range
SRC Input Current
Start-up sequence not completed
Start-up sequence completed
150
150
5
30
30
250
250
10
60
V
µA
µA
r
ON
SRC
r
ON
DRN
SEQUENCING
t
ON
t
DEL1
t
DEL2
t
DEL3
C
DEL
NOTE:
SRC ON-resistance
DRN ON-resistance
Start-up sequence completed
Start-up sequence completed
Turn On Delay
Delay Between V
BOOST
and V
OFF
Delay Between V
ON
and V
OFF
C
DEL
= 100nF (See Figure 22)
C
DEL
= 100nF (See Figure 22)
C
DEL
= 100nF (See Figure 22)
10
10
10
10
22
100
ms
ms
ms
ms
nF
Delay From V
ON
to V
ON
-slice Enabled C
DEL
= 100nF (See Figure 22)
Delay Capacitor
1. Limits should be considered typical and are not production tested.
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