COM20019I 3.3V Rev.C
Cost Competitive
ARCNET (ANSI 878.1)
Controller with 2K x 8
On-Chip RAM
Datasheet
Product Features
New Features:
−
Data Rates up to 312.5 Kbps
−
Programmable Reconfiguration Times
Eight, 256 Byte Pages Allow Four Pages TX and
RX Plus Scratch-Pad Memory
Next ID Readable
Internal Clock Scaler for Adjusting Network
Speed
Operating Temperature Range of -40
o
C to +85
o
C
3.3V power supply with 5V tolerant I/O
Self-Reconfiguration Protocol
Supports up to 255 Nodes
Supports Various Network Topologies (Star,
Tree, Bus...)
CMOS, Single +3.3V Supply
Duplicate Node ID Detection
Powerful Diagnostics
Receive All Packets Mode
Flexible Media Interface:
−
RS485 Differential Driver Interface For Cost
Competitive, Low Power, High Reliability
28 Pin PLCC and 48 Pin TQFP packages; Lead-
Free RoHS Compliant packages also available
Ideal for Industrial/Factory/Building Automation
and Transportation Applications
Deterministic, (ANSI 878.1), Token Passing
ARCNET Protocol
Minimal Microcontroller and Media Interface
Logic Required
Flexible Interface For Use With All
Microcontrollers or Microprocessors
Automatically Detects Type of Microcontroller
Interface
2Kx8 On-Chip Dual Port RAM
Command Chaining for Packet Queuing
Sequential Access to Internal RAM
Software Programmable Node ID
ORDERING INFORMATION
Order Number(s):
COM20019I 3VLJP for 28 pin PLCC * package
COM20019I 3V-DZD for 28 pin PLCC * Lead-Free RoHS Compliant package
COM20019I 3V-HD for 48 pin TQFP package
COM20019I 3V-HT for 48 pin TQFP Lead-Free RoHS Compliant package
* TQFP package is recommended for new design
SMSC COM20019I 3.3V Rev.C
Page 1
Rev. 11-07-08
DATASHEET
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123
Copyright © 2008 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause
or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further
testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale
Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems
Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND
ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY
DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR
REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC
OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO
HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
DAMAGES.
Rev. 11-07-08
Page 2
SMSC COM20019I 3.3V Rev.C
DATASHEET
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
TABLE OF CONTENTS
Chapter 1
Chapter 2
Chapter 3
Chapter 4
4.1
4.2
4.3
4.4
4.5
General Description ............................................................................................................. 6
Pin Configurations ............................................................................................................... 7
Description of Pin Functions ............................................................................................... 9
Protocol Description........................................................................................................... 12
NETWORK PROTOCOL................................................................................................................ 12
DATA RATES................................................................................................................................. 12
NETWORK RECONFIGURATION ................................................................................................ 12
BROADCAST MESSAGES............................................................................................................ 13
EXTENDED TIMEOUT FUNCTION............................................................................................... 13
4.5.1
4.5.2
4.5.3
Response Time.......................................................................................................................................13
Idle Time.................................................................................................................................................13
Reconfiguration Time..............................................................................................................................14
Invitations To Transmit ...........................................................................................................................14
Free Buffer Enquiries..............................................................................................................................14
Data Packets ..........................................................................................................................................15
Acknowledgements.................................................................................................................................15
Negative Acknowledgements .................................................................................................................15
4.6
LINE PROTOCOL .......................................................................................................................... 14
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
Chapter 5
5.1
5.2
5.1.1
5.2.1
5.2.2
5.2.3
System Description............................................................................................................. 16
High Speed CPU Bus Timing Support ....................................................................................................19
Backplane Configuration.........................................................................................................................21
Differential Driver Configuration..............................................................................................................22
Programmable TXEN Polarity.................................................................................................................22
MICROCONTROLLER INTERFACE ............................................................................................. 16
TRANSMISSION MEDIA INTERFACE.......................................................................................... 21
Chapter 6
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10
6.2.11
6.2.12
6.2.13
Functional Description....................................................................................................... 25
Interrupt Mask Register (IMR) ................................................................................................................26
Data Register..........................................................................................................................................27
Tentative ID Register ..............................................................................................................................27
Node ID Register ....................................................................................................................................27
Next ID Register .....................................................................................................................................27
Status Register .......................................................................................................................................27
Diagnostic Status Register .....................................................................................................................28
Command Register.................................................................................................................................28
Address Pointer Registers ......................................................................................................................28
Configuration Register ........................................................................................................................28
Sub-Address Register .........................................................................................................................28
Setup 1 Register .................................................................................................................................28
Setup 2 Register .................................................................................................................................29
Sequential Access Memory ....................................................................................................................37
Access Speed.........................................................................................................................................37
Selecting RAM Page Size.......................................................................................................................38
Transmit Sequence.................................................................................................................................39
Receive Sequence..................................................................................................................................40
Transmit Command Chaining .................................................................................................................42
Receive Command Chaining ..................................................................................................................42
MICROSEQUENCER .................................................................................................................... 25
INTERNAL REGISTERS................................................................................................................ 26
6.3
6.4
INTERNAL RAM ............................................................................................................................ 37
6.3.1
6.3.2
6.4.1
6.4.2
6.4.3
SOFTWARE INTERFACE .............................................................................................................37
6.5
6.6
COMMAND CHAINING.................................................................................................................. 41
6.5.1
6.5.2
RESET DETAILS ........................................................................................................................... 43
Page 3
Rev. 11-07-08
SMSC COM20019I 3.3V Rev.C
DATASHEET
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
6.6.1
Internal Reset Logic................................................................................................................................43
Bus Determination ..................................................................................................................................43
Normal Results: ......................................................................................................................................45
Abnormal Results: ..................................................................................................................................45
6.7
6.8
6.9
7.1
7.2
INITIALIZATION SEQUENCE ....................................................................................................... 43
6.7.1
6.8.1
6.8.2
IMPROVED DIAGNOSTICS .......................................................................................................... 44
OSCILLATOR ................................................................................................................................ 45
Chapter 7
Operational Description .................................................................................................... 47
MAXIMUM GUARANTEED RATINGS* ......................................................................................... 47
DC ELECTRICAL CHARACTERISTICS........................................................................................ 47
Chapter 8
Chapter 9
9.1
9.2
10.1
10.2
Timing Diagrams................................................................................................................ 50
Package Outlines ................................................................................................................ 64
28 Pin PLCC Package Outline and Parameters ............................................................................ 64
48 Pin TQFP Package Outline and Parameters ............................................................................ 65
Chapter 10
Appendix A...................................................................................................................... 66
NOSYNC Bit................................................................................................................................... 66
EF Bit.............................................................................................................................................. 66
Chapter 11
Chapter 12
12.1
Appendix B ...................................................................................................................... 69
Appendix C...................................................................................................................... 70
Software Identification of the COM20019I 3V Rev B and Rev C................................................... 70
Rev. 11-07-08
Page 4
SMSC COM20019I 3.3V Rev.C
DATASHEET
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
LIST OF FIGURES
Figure 3.1 - COM20019I 3V OPERATION ...................................................................................................................11
Figure 5.1 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE ............................................17
Figure 5.2 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE ...................................18
Figure 5.3 - HIGH SPEED CPU BUS TIMING - INTEL CPU MODE............................................................................19
Figure 5.4 - COM20019I 3V NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS .....................................21
Figure 5.5 - INTERNAL BLOCK DIAGRAM ..................................................................................................................23
Figure 6.1 - SEQUENTIAL ACCESS OPERATION ......................................................................................................37
Figure 6.2 - RAM BUFFER PACKET CONFIGURATION .............................................................................................39
Figure 6.3 - COMMAND CHAINING STATUS REGISTER QUEUE ..............................................................................41
Figure 7.1 - AC MEASUREMENTS ..............................................................................................................................49
Figure 8.1 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE .................................................50
Figure 8.2 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE .................................................51
Figure 8.3 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE................................................52
Figure 8.4 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE................................................53
Figure 8.5 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE ........................................54
Figure 8.6 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE ........................................55
Figure 8.7 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE ........................................56
Figure 8.8 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE ........................................57
Figure 8.9 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE ......................................58
Figure 8.10 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE ....................................59
Figure 8.11 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE ....................................61
Figure 10.1 - EFFECT OF THE EB BIT ON THE TA/RI BIT ........................................................................................67
Figure 11.1 - EXAMPLE OF INTERFACE CIRCUIT DIAGRAM TO ISA BUS .............................................................69
LIST OF TABLES
Table 5.1 - Typical Media .............................................................................................................................................24
Table 6.1 - Read Register Summary.............................................................................................................................25
Table 6.2 - Write Register Summary ............................................................................................................................26
Table 6.3 - Status Register ...........................................................................................................................................29
Table 6.4 - Diagnostic Status Register..........................................................................................................................30
Table 6.5 - Command Register.....................................................................................................................................31
Table 6.6 - Address Pointer High Register ....................................................................................................................32
Table 6.7 - Address Pointer Low Register.....................................................................................................................32
Table 6.8 - Sub Address Register .................................................................................................................................33
Table 6.9 - Configuration Register ................................................................................................................................33
Table 6.10 - Setup 1 Register .......................................................................................................................................34
Table 6.11 - Setup 2 Register .......................................................................................................................................35
SMSC COM20019I 3.3V Rev.C
Page 5
Rev. 11-07-08
DATASHEET
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