Si7892BDP-T1-GE3 (Lead (Pb)-free and Halogen-free)
S
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS
T
A
= 25 °C, unless otherwise noted
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (T
J
= 150°C)
a
Pulsed Drain Current (10 µs Pulse Width)
Continuous Source Current (Diode Conduction)
Avalanche Current
Single Pulse Avalanche Energy
Maximum Power Dissipation
a
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
b, c
a
Symbol
V
DS
V
GS
T
A
= 25 °C
T
A
= 70 °C
I
D
I
DM
I
S
I
AS
E
AS
P
D
T
J
, T
stg
10 s
Steady State
30
± 20
Unit
V
25
20
60
4.1
40
80
5
3.2
- 55 to 150
260
15
12
A
1.5
mJ
1.8
1.1
W
°C
L = 0.1 mH
T
A
= 25 °C
T
A
= 70 °C
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambient
a
Maximum Junction-to-Case (Drain)
t
≤
10 s
Steady State
Steady State
Symbol
R
thJA
R
thJC
Typical
20
53
2.1
Maximum
25
70
3.2
Unit
°C/W
Notes:
a. Surface Mounted on 1" x 1" FR4 board.
b. See Solder Profile (http://www.vishay.com/ppg?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and
is not required to ensure adequate bottom side solder interconnection.
c. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
Document Number: 73228
S-80440-Rev. C, 03-Mar-08
www.vishay.com
1
Si7892BDP
Vishay Siliconix
SPECIFICATIONS
T
J
= 25 °C, unless otherwise noted
Parameter
Static
Gate Threshold Voltage
V
DS
Temperature Coefficient
V
GS(th)
Temperature Coefficient
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
a
Drain-Source On-State Resistance
a
Forward Transconductance
a
Diode Forward Voltage
a
Dynamic
b
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Source-Drain Reverse Recovery
Reverse Recovery Charge
Symbol
V
GS(th)
ΔV
DS/Tj
ΔV
GS(th)/Tj
I
GSS
I
DSS
I
D(on)
R
DS(on)
g
fs
V
SD
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
R
g
t
d(on)
t
r
t
d(off)
t
f
t
rr
Q
rr
Test Conditions
V
DS
= V
GS
, I
D
= 250 µA
I
D
= 250 µA
V
DS
= 0 V, V
GS
= ±20 V
V
DS
= 30 V, V
GS
= 0 V
V
DS
= 30 V, V
GS
= 0 V, T
J
= 55°C
V
DS
≥
5 V, V
GS
= 10 V
V
GS
= 10 V, I
D
= 25 A
V
GS
= 4.5 V, I
D
= 22 A
V
DS
= 15 V, I
D
= 25 A
I
S
= 4.5 A, V
GS
= 0 V
Min.
1.0
28
- 6.5
± 100
1
5
30
0.0034
0.0047
85
0.75
3775
630
295
27
11.4
8.1
1.2
20
13
62
20
40
40
0.0042
0.0057
1.2
Typ.
Max.
3.0
Unit
V
mV/°C
nA
µA
A
Ω
S
V
V
DS
= 15 V, V
SS
= 0 V, f = 1 Hz
pF
40
nC
2.0
30
20
100
35
60
60
Ω
V
DS
= 15 V, V
GS
= 4.5 V, I
D
= 25 A
0.5
V
DD
= 15 V, R
L
= 15
Ω
I
D
≅
1 A, V
GEN
= 10 V, R
G
= 6
Ω
ns
I
F
= 2.9 A, di/dt = 100 A/µs
nC
Notes:
a. Pulse test; pulse width
≤
300 µs, duty cycle
≤
2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
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