CY62167E MoBL

®

16-Mbit (1 M × 16 / 2 M × 8) Static RAM

Features

■

Configurable as 1 M × 16 or as 2 M × 8 SRAM

Very high speed: 45 ns

Wide voltage range: 4.5 V to 5.5 V

Ultra low standby power

❐

Typical standby current: 1.5 µA

❐

Maximum standby current: 12 µA

Ultra low active power

❐

Typical active current: 2.2 mA at f = 1 MHz

Easy memory expansion with CE

1

, CE

2

, and OE features

Automatic power-down when deselected

CMOS for optimum speed and power

Offered in 48-pin TSOP I package

and BLE are HIGH). The input and output pins (I/O

0

through

I/O

15

) are placed in a high impedance state when:

■

The device is deselected (CE

1

HIGH or CE

2

LOW)

Outputs are disabled (OE HIGH)

Both byte high enable and byte low enable are disabled (BHE,

BLE HIGH) or

A write operation is in progress (CE

1

LOW, CE

2

HIGH, and WE

LOW)

■

To write to the device, take chip enables (CE

1

LOW and CE

2

HIGH) and write enable (WE) input LOW. If byte low enable

(BLE) is LOW, then data from I/O pins (I/O

0

through I/O

7

), is

written into the location specified on the address pins (A

0

through

A

19

). If byte high enable (BHE) is LOW, then data from the I/O

pins (I/O

8

through I/O

15

) is written into the location specified on

the address pins (A

0

through A

19

).

To read from the device, take chip enables (CE

1

LOW and CE

2

HIGH) and output enable (OE) LOW while forcing the write

enable (WE) HIGH. If byte low enable (BLE) is LOW, then data

from the memory location specified by the address pins appears

on I/O

0

to I/O

7

. If byte high enable (BHE) is LOW, then data from

memory appears on I/O

8

to I/O

15

. See

Truth Table on page 12

for a complete description of read and write modes.

The CY62167E device is suitable for interfacing with processors

that have TTL I/P levels. It is not suitable for processors that

require CMOS I/P levels. Please see

Electrical Characteristics

on page 4

for more details and suggested alternatives.

For a complete list of related documentation, click

here.

Functional Description

The CY62167E is a high performance CMOS static RAM

organized as 1 M words by 16-bits/2 M words by 8-bits. This

device features advanced circuit design to provide an ultra low

active current. This is ideal for providing More Battery Life

(MoBL

®

) in portable applications. The device also has an

automatic power down feature that reduces power consumption

when addresses are not toggling. Place the device into standby

mode when deselected (CE

1

HIGH, or CE

2

LOW, or both BHE

Logic Block Diagram

A

10

A

9

A

8

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

DATA IN DRIVERS

ROW DECODER

1 M × 16 / 2 M × 8

RAM ARRAY

SENSE AMPS

I/O

0

–I/O

7

I/O

8

–I/O

15

COLUMN DECODER

CE

2

POWER DOWN

CIRCUIT

A

11

A

12

A

13

A

14

A

15

A

16

A

17

A

18

A

19

CE

1

BHE

BLE

BYTE

BHE

WE

OE

BLE

CE

2

CE

1

Cypress Semiconductor Corporation

Document Number: 001-15607 Rev. *G

•

198 Champion Court

•

San Jose

,

CA 95134-1709

•

408-943-2600

Revised July 20, 2015

CY62167E MoBL

®

Contents

Pin Configuration ............................................................. 3

Product Portfolio .............................................................. 3

Maximum Ratings ............................................................. 4

Operating Range ............................................................... 4

Electrical Characteristics ................................................. 4

Capacitance ...................................................................... 5

Thermal Resistance .......................................................... 5

AC Test Loads and Waveforms ....................................... 5

Data Retention Characteristics ....................................... 6

Data Retention Waveform ................................................ 6

Switching Characteristics ................................................ 7

Switching Waveforms ...................................................... 8

Truth Table ...................................................................... 12

Ordering Information ...................................................... 13

Ordering Code Definitions ......................................... 13

Package Diagram ............................................................ 14

Acronyms ........................................................................ 15

Document Conventions ................................................. 15

Units of Measure ....................................................... 15

Document History Page ................................................. 16

Sales, Solutions, and Legal Information ...................... 18

Worldwide Sales and Design Support ....................... 18

Products .................................................................... 18

PSoC® Solutions ...................................................... 18

Cypress Developer Community ................................. 18

Technical Support ..................................................... 18

Document Number: 001-15607 Rev. *G

Page 2 of 18

CY62167E MoBL

®

Pin Configuration

48-pin TSOP I pinout (

Top View)

[1, 2]

A15

A14

A13

A12

A11

A10

A9

A8

A19

NC

WE

CE

2

NC

BHE

BLE

A18

A17

A7

A6

A5

A4

A3

A2

A1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE

Vss

I/O15/A20

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

Vcc

I/O11

I/O3

I/O10

I/O2

I/O9

I/O1

I/O8

I/O0

OE

Vss

CE1

A0

Product Portfolio

Power Dissipation

Product

Min

CY62167ELL

4.5

V

CC

Range (V)

Typ

[3]

5.0

Max

5.5

45

Speed

(ns)

Operating I

CC

(mA)

f = 1 MHz

Typ

[3]

2.2

Max

4.0

25

f = f

max

Typ

[3]

Max

30

Standby I

SB2

(µA)

Typ

[3]

1.5

Max

12

Notes

1. NC pins are not connected on the die.

2. The BYTE pin in the 48-pin TSOPI package must be tied to V

CC

to use the device as a 1 M × 16 SRAM. The 48-TSOPI package can also be used as a 2 M × 8

SRAM by tying the BYTE signal to V

SS

. In the 2 M × 8 configuration, pin 45 is A20, while BHE, BLE and I/O

8

to I/O

14

pins are not used.

3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V

CC

= V

CC(typ)

, T

A

= 25 °C.

Document Number: 001-15607 Rev. *G

Page 3 of 18

CY62167E MoBL

®

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device. User guidelines are not tested.

Storage temperature ................................ –65 °C to +150 °C

Ambient temperature

with power applied ................................... –55 °C to +125 °C

Supply voltage to ground potential

[4, 5]

DC input voltage

[4, 5]

.....................................–0.5 V to 6.0 V

Output current into outputs (LOW) ............................. 20 mA

Static discharge voltage

(MIL-STD-883, method 3015) ................................. >2001 V

Latch-up current ..................................................... >200 mA

.........–0.5 V to 6.0 V

Operating Range

Device

CY62167ELL

Range

Industrial

Ambient

Temperature

V

CC

[6]

DC voltage applied to outputs

in high Z state

[4, 5]

.........................................–0.5 V to 6.0 V

–40 °C to +85 °C 4.5 V to 5.5 V

Electrical Characteristics

Over the Operating Range

Parameter

V

OH

V

OL

V

IH

V

IL

I

IX

I

OZ

I

CC

I

SB2[10]

Description

Output HIGH voltage

Output LOW voltage

Input HIGH voltage

Input LOW voltage

Input leakage current

Output leakage current

V

CC

operating supply current

Test Conditions

V

CC

= 4.5 V

V

CC

= 5.5 V

I

OL

= 2.1 mA

V

CC

= 4.5 V to 5.5 V

V

CC

= 4.5 V to 5.5 V

GND < V

I

< V

CC

GND < V

O

< V

CC

, output disabled

f = f

MAX

= 1/t

RC

f = 1 MHz

Automatic power down

current—CMOS inputs

V

CC

= V

CC(max)

I

OUT

= 0 mA

CMOS levels

I

OH

= –1.0 mA

I

OH

= –0.1 mA

45 ns

Min

2.4

–

2.2

–0.5

–1

–

Typ

[7]

–

25

2.2

1.5

Max

–

3.4

[8]

0.4

V

CC

+ 0.5 V

0.7

[9]

+1

30

4.0

12

V

µA

mA

µA

Unit

V

CE

1

> V

CC

– 0.2 V or CE

2

< 0.2 V, or

BHE and BLE > V

CC

– 0.2 V,

V

IN

> V

CC

– 0.2 V or V

IN

< 0.2 V,

f = 0, V

CC

= V

CC

(max)

Notes

4. V

IL

(min) = –2.0 V for pulse durations less than 20 ns.

5. V

IH

(max) = V

CC

+ 0.75 V for pulse durations less than 20 ns.

6. Full Device AC operation is based on a 100 µs ramp time from 0 to V

CC

(min) and 200 µs wait time after V

CC

stabilization.

7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V

CC

= V

CC

(typ), T

A

= 25 °C.

8. Please note that the maximum VOH limit does not exceed minimum CMOS VIH of 3.5 V. If you are interfacing this SRAM with 5 V legacy processors that require a

minimum VIH of 3.5V, please refer to Application Note

AN6081

for technical details and options you may consider.

9. Under DC conditions the device meets a V

IL

of 0.8 V. However, in dynamic conditions input LOW voltage applied to the device must not be higher than 0.7 V.

10. Chip enables (CE

1

and CE

2

), byte enables (BHE and BLE) and BYTE need to be tied to CMOS levels to meet the I

SB2

/ I

CCDR

spec. Other inputs can be left floating.

Document Number: 001-15607 Rev. *G

Page 4 of 18

CY62167E MoBL

®

Capacitance

Parameter

[11]

C

IN

C

OUT

Description

Input capacitance

Output capacitance

Test Conditions

T

A

= 25 °C, f = 1 MHz, V

CC

= V

CC(typ)

Max

10

Unit

pF

Thermal Resistance

Parameter

[11]

Θ

JA

Θ

JC

Description

Thermal resistance

(junction to ambient)

Thermal resistance

(junction to case)

Test Conditions

Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit

board

48-pin TSOP I Unit

54.25

12.63

°C/W

AC Test Loads and Waveforms

Figure 1. AC Test Loads and Waveforms

V

CC

OUTPUT

R1

V

CC

GND

10%

R2

ALL INPUT PULSES

90%

10%

FALL TIME= 1 V/ns

30 pF

INCLUDING

JIG AND

SCOPE

RISE TIME= 1 V/ns

EQUIVALENT TO: THÉVENIN EQUIVALENT

R

TH

OUTPUT

V

TH

Parameters

R1

R2

R

TH

V

TH

Values

1800

990

639

1.77

Unit

Ω

V

Note

11. Tested initially and after any design or process changes that may affect these parameters.

Document Number: 001-15607 Rev. *G

Page 5 of 18

参数名称	属性值
Product Attribute	Attribute Value
制造商 Manufacturer	Cypress(赛普拉斯)
产品种类 Product Category	SRAM
RoHS	Details
Memory Size	16 Mbit
Organization	1 M x 16, 2 M x 8
Access Time	45 ns
接口类型 Interface Type	Parallel
电源电压-最大 Supply Voltage - Max	5.5 V
电源电压-最小 Supply Voltage - Min	4.5 V
Supply Current - Max	30 mA
最小工作温度 Minimum Operating Temperature	- 40 C
最大工作温度 Maximum Operating Temperature	+ 85 C
安装风格 Mounting Style	SMD/SMT
封装 / 箱体 Package / Case	TSOP-48
系列 Packaging	Reel
数据速率 Data Rate	SDR
高度 Height	1.2 mm
长度 Length	18.4 mm
Memory Type	SDR
工作温度范围 Operating Temperature Range	- 40 C to + 85 C
类型 Type	Asynchronous
宽度 Width	12 mm
Number of Ports	1
Moisture Sensitive	Yes
工厂包装数量 Factory Pack Quantity	1000

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