Operating Temperature Range ........................... -40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................ -65°C to +150°C
Lead Temperature (soldering, 10s) ................................. +300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
(Note 1)
TQFN
Junction-to-Ambient Thermal Resistance (θ
JA
).... ......28°C/W
Junction-to-Case Thermal Resistance (θ
JC
) ..... ....... 1.4°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
PARAMETER
ANALOG INPUT
Input Voltage Range (Note 3)
Absolute Input Voltage Range
Common-Mode Input Range
Input Leakage Current
Input Capacitance
STATIC PERFORMANCE (Note 4)
Resolution
Resolution
No Missing Codes
Offset Error (Note 4)
Offset Temperature Coefficient
Gain Error
Gain Error Temperature
Coefficient (Note 5)
Gain Error
Gain Error Temperature
Coefficient (Note 5)
Integral Nonlinearity
(f
SAMPLE
= 1Msps, V
AVDD
= 1.8V, V
DVDD
= 1.8V, V
OVDD
= 1.5V to 3.6V, V
REFVDD
= 3.6V, V
REF
= 3.3V, Internal Ref Buffers On,
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
SYMBOL
CONDITIONS
(AIN_+) - (AIN_-)
AIN_+, AIN_- relative to AGND
[(AIN_+) + (AIN_-)]/2
Acquisition phase
MIN
-V
REF
-0.1
V
REF
/2 -
0.1
-1
V
REF
/2
0.001
32
N
LSB
V
REF
= 3.3V
20
-15
Referred to REFIN reference input
Referred to REFIN reference input
Referred to REF1 or REF2 pins
Referred to REF1 or REF2 pins
INL
-5
-50
-175
±1
±0.1
±20
±0.2
±10
±0.12
±1.5
+5
+50
+175
+15
20
6.3
TYP
MAX
+V
REF
V
REF
+
0.1
V
REF
/2
+ 0.1
+1
UNITS
V
V
V
µA
pF
Bits
µV
Bits
LSB
LSB/°C
LSB
LSB/°C
LSB
LSB/°C
LSB
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Maxim Integrated
│
2
MAX11960
Dual Simultaneous Sampling, 20-Bit, 1Msps,
Differential SAR ADC
Electrical Characteristics (continued)
(f
SAMPLE
= 1Msps, V
AVDD
= 1.8V, V
DVDD
= 1.8V, V
OVDD
= 1.5V to 3.6V, V
REFVDD
= 3.6V, V
REF
= 3.3V, Internal Ref Buffers On,
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
Differential Nonlinearity (Note
6)
Analog Input CMR
Power-Supply Rejection (Note
7)
Power-Supply Rejection (Note
7)
Transition Noise
EXTERNAL REFERENCE
REF1_, REF2_ Voltage Input
Range
Load Current
REF1_, REF2_ Input
Capacitance
REFERENCE BUFFER
REFIN Input Voltage Range
REFIN Input Current
Turn-On Settling Time
External Compensation
Capacitor
Dynamic Range
Signal-to-Noise Ratio
Signal-to-Noise Plus Distortion
Spurious-Free Dynamic Range
Total Harmonic Distortion
Total Harmonic Distortion
Total Harmonic Distortion
Crosstalk
SAMPLING DYNAMICS
Throughput
Full-Power Bandwidth
Acquisition Time
t
ACQ
-3dB point
-0.1dB point
150
0
20
3
1
Msps
MHz
ns
SNR
SINAD
SFDR
THD
THD
THD
XTLK
C
EXT
V
REF
I
REF
1Msps, V
REF
= 3.3V
2.5
SYMBOL
DNL
CMR
PSR
PSR
DC
PSR vs. AVDD
PSR vs. REFVDD
CONDITIONS
MIN
-0.9
TYP
±0.5
16
2
3
4
3.3
600
1
V
REFVDD
- 200mV
3.6
MAX
+0.9
UNITS
LSB
LSB/V
LSB/V
LSB/V
LSB
RMS
V
µA
nF
V
REFIN
I
REFIN
V
REF
< (V
REFVDD
- 200mV)
2.5
3
1
V
nA
ms
µF
C
EXT
= 10µF on REF_ pin,
C
REFIN
= 0.1µF on REFIN pin
REF_ pins
4.7
20
10
DYNAMIC PERFORMANCE (Note 8)
Internal RefBuffer, -60dBFS input
Internal RefBuffer, f
IN
= 10kHz
Internal RefBuffer, f
IN
= 10kHz,
-0.1dBFs
Internal RefBuffer, f
IN
= 10kHz
Internal RefBuffer, f
IN
= 10kHz
Internal RefBuffer, f
IN
= 100kHz
Internal RefBuffer, f
IN
= 250kHz
98
98
99.0
99
99
125
-123
-115
-107
-120
dB
dB
dB
dB
dB
dB
dB
dB
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Maxim Integrated
│
3
MAX11960
Dual Simultaneous Sampling, 20-Bit, 1Msps,
Differential SAR ADC
Electrical Characteristics (continued)
(f
SAMPLE
= 1Msps, V
AVDD
= 1.8V, V
DVDD
= 1.8V, V
OVDD
= 1.5V to 3.6V, V
REFVDD
= 3.6V, V
REF
= 3.3V, Internal Ref Buffers On,
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
Aperture Delay
Aperture Jitter
POWER SUPPLIES
Analog Supply Voltage
Digital Supply Voltage
Reference Buffer Supply
Voltage
Interface Supply Voltage
Analog Supply Current
Digital Supply Current
Reference Buffer Supply
Current
Reference Buffer Supply
Current
Interface Supply Current
(Note 9)
Shutdown Current
Shutdown Current
Power Dissipation
DIGITAL INPUTS (DIN_, SCLK, CNVST_)
Input Voltage High
Input Voltage Low
Input Capacitance
Input Current
DIGITAL OUTPUTS (DOUT_)
Output Voltage High
Output Voltage Low
V
OH
V
OL
I
SOURCE
= 2mA
I
SINK
= 2mA
V
OVDD
-
0.4
0.4
V
V
V
IH
V
IL
C
IN
I
IN
V
IN
= 0V or V
OVDD
V
OVDD
= 1.5V to 3.6V
V
OVDD
= 1.5V to 3.6V
10
1
0.7 x
V
OVDD
0.3 x
V
OVDD
V
V
pF
µA
AVDD
DVDD
REFVDD
OVDD
I
AVDD
I
DVDD
I
REFVDD
I
REFVDD
I
OVDD
V
AVDD
= 1.8V
V
DVDD
= 1.8V
V
REFVDD
= 3.6V, internal buffers
enabled
V
REFVDD
= 3.6V, internal buffers
powered down
V
OVDD
= 1.5V
V
OVDD
= 3.6V
For AVDD, DVDD, REFVDD
For DVDD
V
AVDD
= 1.8V, V
DVDD
= 1.8V,
V
REFVDD
= 3.3V, internal reference
buffers disabled
1.7
1.7
2.7
1.5
3.8
3.0
6
0.4
0.54
2
2
2
13.56
16.44
1.8
1.8
3.3
1.9
1.9
3.6
3.6
4.8
3.6
7.2
V
V
V
V
mA
mA
mA
mA
mA
µA
µA
mW
SYMBOL
CONDITIONS
Time delay from CNVST_ rising edge
to time at which sample is taken for
conversion
MIN
TYP
1
3
MAX
UNITS
ns
ps
RMS
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Maxim Integrated
│
4
MAX11960
Dual Simultaneous Sampling, 20-Bit, 1Msps,
Differential SAR ADC
Electrical Characteristics (continued)
(f
SAMPLE
= 1Msps, V
AVDD
= 1.8V, V
DVDD
= 1.8V, V
OVDD
= 1.5V to 3.6V, V
REFVDD
= 3.6V, V
REF
= 3.3V, Internal Ref Buffers On,
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
TIMING
DIN_ to SCLK Rising-Edge
Setup
DIN_ to SCLK Rising-Edge
Hold
DOUT_ End-Of-Conversion
Low Time
DOUT_ to SCLK Rising-Edge
Hold
DOUT_ to SCLK Rising-Edge
Setup
SCLK High
SCLK Period
SCLK Low
CNVST_ Rising-Edge To SCLK
Rising Edge
SCLK Rising-Edge to CNVST_
Rising Edge
CNVST_ High
CNVST_ High to EOC
Conversion Period
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
1000
100MHz SCLK
1
15
2.5
1.5
4.5
10
4.5
0
25
25
850
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Note 2:
Limits are 100% production tested at T
A
= +25°C. Limits over the operating temperature range are guaranteed by design
and device characterization.
Note 3:
See the
Analog Inputs
section.
Note 4:
See the
Definitions
section at the end of the data sheet.
Note 5:
See the
Definitions
section at the end of the data sheet. Error contribution from the external reference not included.
Note 6:
Parameter is guaranteed by design.
Note 7:
Defined as the change in positive full-scale code transition caused by a ±5% variation in the supply voltage.
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