DATASHEET
ISL15100
Single Port, PLC Differential Line Driver
The ISL15100 is a single port differential line driver developed
for Power Line Communication (PLC) applications. The device
is designed to drive heavy line loads while maintaining the
high level of linearity required in OFDM PLC modem links. With
15.5dBm of total transmit signal power into 100 line load,
the driver achieves -43dB average MTPR distortion across the
output spectrum up to 86MHz.
The ISL15100 has two bias current control pins (C0, C1) to
allow for four power settings (disable, low, medium, high). In
disable mode, the line driver outputs maintain a high
impedance in the presence of high receive signal amplitude,
so it doesn’t affect TDM receive signal integrity.
The ISL15100 is available in the thermally-enhanced 16 Ld
QFN and is specified for operation over the full -40°C to +85°C
ambient temperature range.
FN8577
Rev 0.00
September 19, 2013
Features
• Single differential driver
• 100MHz Broadband PLC G.hn, EOC, HomePlug AV2
• Control pins for enable/disable and supply current selection
• High output impedance when disabled for TDM operation
• -43dBc average MTPR distortion at full line power
• Single +12V or bipolar ±6V nominal supplies
• High surge current handling capability
Applications
• Power Line Communication differential driver
• Pin compatible upgrade to ISL1571IRZ
Related Literature
•
AN1325
“Choosing and Using Bypass Capacitors”
TABLE 1. ALTERNATE SOLUTIONS
PART #
ISL1571
NOMINAL ±V
S
(V)
±6, +12
BANDWIDTH
(MHz)
200
APPLICATIONS
HomePlug AV1
+12V
SUPPLY
DECOUPLING
NOT SHOW N
100n
500
+
½ ISL15100
-30
3.9
-40
1:2
-
AFE
Rg
133
2.2n
Rf
1k
Rf
1k
-50
-60
POWER (dBM)
Vcm
100
NOMINAL
LINE
-70
-80
-90
-100
-110
-120
-130
2
7
12
17
22
27
32
37
42
47
-
½ ISL15100
500
100n
3.9
+
TYPICAL DIFFERENTIAL I/O LINE DRIVER
FREQUENCY (MHz)
FIGURE 1. TYPICAL APPLICATION CIRCUIT
FIGURE 2. 50MHz PLC SPECTRUM
FN8577 Rev 0.00
September 19, 2013
Page 1 of 9
ISL15100
Connection Diagram
+12V
INA+
+
½ ISL15100
P
LINE
= 16dBm
CF = 15.4dB
Av = 1 + 2 x 1000 = 16(V/V)
133
140DIFFERENTIAL RECEIVER
PATH LOAD AT TXMN INPUT
3.9
+
+
OUTA
500
-
1k
1:2
INA-
500mVp +6V
133
INB-
8.0Vp
11.8Vp
INTO P
LINE
100
-
500
½ ISL15100
1k
Txmn
OUTB
3.9
INB+
+
BIAS
CURRENT
CONTROL
C0
C1
FIGURE 3. TYPICAL DIFFERENTIAL AMPLIFIER I/O
Ordering Information
PART
NUMBER
(Notes 2, 3)
ISL15100IRZ
ISL15100IRZ-T7 (Note 1)
ISL15100IRZ-T13 (Note 1)
ISL15100EVAL1Z
NOTES:
1. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL15100.
For more information on MSL please see tech brief
TB363.
PART
MARKING
151 00IRZ
151 00IRZ
151 00IRZ
Evaluation Board
TEMP RANGE
(°C)
-40 to +85
-40 to +85
-40 to +85
PACKAGE
(Pb-free)
16 Ld QFN
16 Ld QFN
16 Ld QFN
PKG.
DWG. #
L16.4x4H
L16.4x4H
L16.4x4H
FN8577 Rev 0.00
September 19, 2013
Page 2 of 9
ISL15100
Pin Configuration
ISL15100
(16 LD QFN)
TOP VIEW
OUTB
13
12 NC
11 INB-
EP*
10 INB+
9
5
NC
6
NC
7
VS-
8
C0
C1
OUTA
VS+
14
NC
15
16
NC 1
INA- 2
INA+ 3
GND 4
*EXPOSED THERMAL PAD CONNECTS TO MOST NEGATIVE SUPPLY
Pin Descriptions
PIN NUMBER
EP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN NAME
THERMAL PAD
NC
INA-
INA+
GND
NC
NC
V
S
-
C0
C1
INB+
INB-
NC
OUTB
V
S
+
NC
OUTA
No Internal Connection
Amplifier A Inverting Input
Amplifier A Non-Inverting Input
Ground
No Internal Connection
No Internal Connection
Negative Supply Voltage (-6V for split supplies, GND for single supply operation)
Digital Control Pin
Digital Control Pin
Amplifier B Non-Inverting Input
Amplifier B Inverting Input
No Internal Connection
Amplifier B Output
Positive Supply Voltage (+6V for split supplies, +12V for single supply operation)
No Internal Connection
Amplifier A Output
FUNCTION
Connect to the Most Negative Supply
C0, C1 Truth Table
C1
0
0
1
1
C0
0
1
0
1
High Bias Setting
Medium Bias Setting
Low Bias Setting
Outputs Disabled (Power Down)
FUNCTION
FN8577 Rev 0.00
September 19, 2013
Page 3 of 9
ISL15100
Absolute Maximum Ratings
(T
A
= +25°C)
V
S
+ Voltage to V
S
- or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +13.3V
INA+, INB+ Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to V
S
+
C
0
, C
1
Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
S
+
Current into any Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA
Continuous Output Current for Long Term Reliability. . . . . . . . . . . . . . . . 50mA
Latch-up (Tested per JESD78D, Class II) . . . . . . . . . . . . . . . . . . . . . . 100mA
ESD Rating
Human Body Model (Tested per JESD22-A114F). . . . . . . . . . . . . . . . . . 4kV
Charge Device Model (Tested per JESD22-C101E). . . . . . . . . . . . . 1.5kV
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . 300V
Thermal Information
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
16 Ld QFN Package (Notes 4, 5) . . . . . . . .
53
16.5
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . -40°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . - 40°C to +150°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief
TB379.
5. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
DYNAMIC PERFORMANCE
-3dB Bandwidth
Slew Rate
Total Harmonic Distortion
V
S
+ = +12V, V
S
- = GND = 0V, see Figure 3, Full Bias (C
0
= C
1
= 0V), T
A
= +25°C, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
BW
SR
Figure 3, 2V
P-P
differential output at pins
Differential V
OUT
(V
OUTA
- V
OUTB
) from -5V
to +5V (10V
P-P)
180
1200
-88
-72
-64
-51
-43
-55
6
13
50
-67
-68
-58
-48
MHz
V/µs
dBc
dBc
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
THD, Low Frequency, 200kHz, differential 12V
P-P
, across
≥350Ω
Light Load
differential load
THD, Low Frequency, 200kHz, differential 12V
P-P
, across 29Ω
differential load
Heavy Load
THD, High Frequency, 4MHz, differential 12V
P-P
, across
≥350Ω
Light Load
differential load
THD, High Frequency, 4MHz, differential 12V
P-P
, across 29Ω
Heavy Load
differential load
Avg. Multi-Tone Power Ratio
Off State Multi-Tone Power Ratio
Non-inverting Input Spot Voltage Noise
Non-inverting Input Spot Current Noise
Inverting Input Spot Current Noise
DC AND INPUT CHARACTERISTICS
Non-Inverting Input Bias Current
Non-Inverting Input Bias Current
Mismatch
Inverting Input Bias Current
MTPR
MTPR-OFF
Eni
Ini+
Ini-
2MHz to 50MHz, 25kHz tone spacing,
P
LINE
= 15.5dBm, CF = 15dB
2MHz to 50MHz, 25kHz tone spacing,
P
LINE
= 15.5dBm, CF = 15dB
F > 1MHz, spot noise voltage on INA+ and
INB+ inputs separately
F > 1MHz, spot noise current on INA+ and
INB+ inputs separately
F > 1MHz, spot noise current on INA- and
INB- inputs separately
I
B+
I
B+DM
I
B-
Non-inverting inputs, INA+ and INB+, at
mid-supply voltage (Note 7)
Difference between the INA+ and INB+
bias currents
Inverting inputs, INA- and INB-, at mid
supply voltage (Note 7)
-7
-0.5
-90
2
0
-30
7
0.5
55
µA
µA
µA
FN8577 Rev 0.00
September 19, 2013
Page 4 of 9
ISL15100
Electrical Specifications
PARAMETER
Inverting Input Bias Current Mismatch
Inverting Input Bias Current Common
Mode
Input Offset Voltage
Input Offset Voltage Mismatch
Input Offset Voltage Common Mode
Differential Mode Output Offset Voltage
Common Mode Output Offset Voltage
Input Headroom to Positive Supply
Input Headroom to Negative Supply
OUTPUT CHARACTERISTICS
Output Swing
V
S
+ = +12V, V
S
- = GND = 0V, see Figure 3, Full Bias (C
0
= C
1
= 0V), T
A
= +25°C, unless otherwise specified.
DESCRIPTION
I
B-DM
I
B-CM
V
IOA,
V
IOB
V
IODM
V
IOCM
V
OSDM
V
OSCM
(V
S
+) - V
IN(MAX)
V
IN(MIN)
- (V
S
-)
CONDITIONS
Difference between the INA- and INB- input
bias currents
Average inverting input bias currents
(Note 7)
Voltage difference from INA+ to INA- and
from INB+ to INB-
V
IOA
- V
IOB
Average offset voltage across the two
inputs
Output referred total effect of all
differential DC error terms
Output referred total effect of all common
mode DC errors
INA+ and INB+ required margin to V
S
+
supply
INA+ and INB+ required margin to V
S
-
supply
MIN
(Note 6)
-35
-90
-85
-5
-80
-7.8
-105
TYP
0
-30
0
0
20
0
40
3
3
MAX
(Note 6)
35
55
85
5
80
7.8
145
UNIT
µA
µA
mV
mV
mV
mV
mV
V
V
V
O-OPEN
V
O-LOADED
V
S
= ±6V, Differential R
LOAD
≥
1kΩ, each
output pin voltage range
V
S
= ±6V, V
O
in linear region, Differential
R
LOAD
= 29Ω, each output pin voltage
range.
V
S
= ±6V, V
O
driven into the rail, differential
R
LOAD
= 29Ω, each output pin voltage
range.
±4.85
±5.0
±4.6
V
V
±4.2
±4.7
V
Output Current
POWER SUPPLY
Bipolar Supply Range
Single Supply Range
Positive Supply Currents
I
O
Linear output current (not short circuit)
±300
±400
mA
±V
S
V
S
+
I
S
+ (Full bias)
I
S
+ (Medium bias)
I
S
+ (Low bias)
I
S
+ (Power down)
Symmetric supply, pin 4 at GND for logic
reference
Single supply with V
S
- and pin 4 at GND
V
O(DIFF)
= 0V, C
0
= C
1
= 0V
V
O(DIFF)
= 0V, C
0
= 3.3V, C
1
= 0V
V
O(DIFF)
= 0V, C
0
= 0V, C
1
= 3.3V
C
0
= C
1
= 3.3V
C
0
= C
1
= 3.3V (Note 7)
C
0
= C
1
= 0V (Note 7)
Pin 4 at GND, logic reference pin
Pin 4 at GND, logic reference pin
±4
8
27
19
12
5.5
-150
-1.5
2
-0.3
±6
12
32
23
15
7
-90
1
3.3
0
±6.6
13.2
37
26
18
8.5
-30
1.5
5.5
0.8
V
V
mA
mA
mA
mA
µA
µA
V
V
C
0
, C
1
Input High Current
C
0
, C
1
Input Low Current
C
0
, C
1
Logic High Voltage
C
0
, C
1
Logic Low Voltage
NOTES:
I
INH
, C
0
or C
1
I
INL
, C
0
or C
1
V
INH
V
INL
6. Compliance to data sheet limits is assured by one or more methods: production test, characterization and/or design.
7. Positive currents flow out of the pin.
FN8577 Rev 0.00
September 19, 2013
Page 5 of 9
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