IS62WV12816DALL/DBLL
IS65WV12816DALL/DBLL
128K x 16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
FEATURES
•
•
•
•
•
•
•
•
•
•
High-speed access time: 35ns, 45ns, 55ns
CMOS low power operation
– 36 mW (typical) operating
– 9 µW (typical) CMOS standby
TTL compatible interface levels
Single power supply
– 1.8V ± 10% V
dd
(IS62/65WV12816dALL)
– 2.5V--3.6V V
dd
(IS62/65WV12816dBLL)
Fully static operation: no clock or refresh
required
Three state outputs
Data control for upper and lower bytes
Industrial and Autotmovie temperature support
2CS Option Available
Lead-free available
JUNE 2013
2M bit static RAMs organized as 128K words by 16
bits. It is fabricated using
ISSI
's high-performance
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields high-
performance and low power consumption devices.
When
CS1
is HIGH (deselected) or when CS2 is LOW
(deselected) or when
CS1 is LOW, CS2 is HIGH and both
LB and UB are HIGH, the device assumes a standby mode
at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory. A
data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IS62/65WV12816DALL/DBLL are packaged in the
JEDEC standard 48-pin mini BGA (6mm x 8mm) and 44-
Pin TSOP (TYPE II).
DESCRIPTION
The
ISSI
IS62/65WV12816DALL/DBLL are high-speed,
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K x 16
MEMORY ARRAY
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CS2
CS1
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
05/29/2013
1
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
PIN CONFIGURATIONS
48-Pin mini BGA (6mm x 8mm)
(Package Code B)
1
2
3
4
5
6
48-Pin mini BGA (6mm x 8mm)
2 CS Option (Package Code B2)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
LB
I/O
8
I/O
9
GND
V
DD
I/O
14
I/O
15
NC
OE
UB
I/O
10
I/O
11
I/O
12
I/O
13
NC
A8
A0
A3
A5
NC
NC
A14
A12
A9
A1
A4
A6
A7
A16
A15
A13
A10
A2
CSI
I/O
1
I/O
3
I/O
4
I/O
5
WE
A11
N/C
I/O
0
I/O
2
V
DD
GND
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
LB
I/O
8
I/O
9
GND
VDD
I/O
14
I/O
15
NC
OE
UB
I/O
10
I/O
11
I/O
12
I/O
13
NC
A8
A0
A3
A5
NC
NC
A14
A12
A9
A1
A4
A6
A7
A16
A15
A13
A10
A2
CS1
I/O
1
I/O
3
I/O
4
I/O
5
WE
A11
CS2
I/O
0
I/O
2
VDD
GND
I/O
6
I/O
7
NC
44-Pin mini TSOP (Type II)
(Package Code T)
PIN DESCRIPTIONS
A0-A16 Address Inputs
I/O0-I/O15
Data Inputs/Outputs
CS1, CS2
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
LB
Lower-byte Control (I/O0-I/O7)
UB
Upper-byte Control (I/O8-I/O15)
NC
No Connection
Power
V
dd
GND
Ground
A4
A3
A2
A1
A0
CS1
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/29/2013
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
TRUTH TABLE
Mode
Not Selected
WE
X
X
X
H
H
H
H
H
L
L
L
CS1
CS2
OE
H
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
L
L
L
X
X
X
LB
X
X
H
L
X
L
H
L
L
H
L
UB
X
X
H
X
L
H
L
L
H
L
L
I/O PIN
I/O0-I/O7
I/O8-I/O15
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
d
out
High-Z
d
out
d
In
High-Z
d
In
High-Z
High-Z
High-Z
d
out
d
out
High-Z
d
In
d
In
V
DD
Current
I
SB
1
, I
SB
2
I
SB
1
, I
SB
2
I
SB
1
, I
SB
2
I
cc
I
cc
I
cc
Output Disabled
Read
Write
I
cc
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
term
t
Stg
P
t
Parameter
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
Value
–0.2 to V
dd
+0.3
–65 to +150
1.0
Unit
V
°C
W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
OPERATING RANGE (V
DD
)
Range
Commercial
Industrial
Automotive
Ambient Temperature
0°C to +70°C
–40°C to +85°C
-40°C to +125°C
IS62WV12816DALL
1.8V ± 10%
1.8V ± 10%
IS65WV12816DALL
1.8V ± 10%
IS62WV12816DBLL
2.5V - 3.6V
2.5V - 3.6V
IS65WV12816DBLL
2.5V - 3.6V
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/29/2013
3
IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
V
oH
V
oL
V
IH
V
IL
I
LI
I
Lo
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Output Leakage
Test Conditions
I
oH
=
-0.1 mA
I
oH
=
-1 mA
I
oL
=
0.1 mA
I
oL
=
1.0 mA
GND ≤ V
In
≤
V
dd
GND ≤ V
out
≤
V
dd
,
Outputs Disabled
V
DD
1.8V ± 10%
2.5-3.6V
1.8V ± 10%
2.5-3.6V
1.8V ± 10%
2.5-3.6V
1.8V ± 10%
2.5-3.6V
Min.
1.4
2.2
—
—
1.4
2.2
–0.2
–0.2
–1
–1
Max.
—
—
0.2
0.4
V
dd
+ 0.2
V
dd
+ 0.3
0.4
0.6
1
1
Unit
V
V
V
V
V
V
V
V
µA
µA
Notes:
For IS62/65WV12816DALL:
V
IL
(min.) = -1.0V Ac (pluse width < 10ns). Not 100% tested.
V
IH
(max.) = V
dd
+ 1.0V Ac; (pluse width < 10ns). Not 100% tested.
For IS62/65WV12816DBLL:
V
IL
(min.) = -2.0V Ac (pluse width < 10ns). Not 100% tested.
V
IH
(max.) = V
dd
+ 2.0V Ac; (pluse width < 10ns). Not 100% tested.
CAPACITANCE
(1)
Symbol
c
In
c
out
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
V
In
= 0V
V
out
= 0V
Max.
8
10
Unit
pF
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/29/2013
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