CY2308
3.3 V Zero Delay Buffer
3.3 V Zero Delay Buffer
Features
■
■
■
■
■
■
■
■
■
Zero input-output propagation delay, adjustable by capacitive
load on FBK input
Multiple configurations, see
Available CY2308 Configurations
on page 4
for more details
Multiple low skew outputs
Two banks of four outputs, three-stateable by two select inputs
10 MHz to 133 MHz operating range
75 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
Space saving 16-pin 150 mil SOIC package or 16-pin TSSOP
3.3 V operation
Industrial temperature available
The CY2308 has two banks of four outputs each that is controlled
by the select inputs as shown in the table
Select Input Decoding
on page 3.
If all output clocks are not required, Bank B is
three-stated. The input clock is directly applied to the output for
chip and system testing purposes by the select inputs.
The CY2308 PLL enters a power down state when there are no
rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off resulting in less than 25
A
of current draw. The PLL shuts down in two additional cases as
shown in the table
Select Input Decoding on page 3.
Multiple CY2308 devices accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is less than 700 ps.
The CY2308 is available in five different configurations as shown
in the table
Available CY2308 Configurations on page 4.
■
Functional Description
The CY2308 is a 3.3 V Zero Delay Buffer designed to distribute
high speed clocks in PC, workstation, datacom, telecom, and
other high performance applications.
The part has an on-chip PLL that locks to an input clock
presented on the REF pin. The PLL feedback is driven from
external FBK pin, so user has flexibility to choose any one of the
outputs as feedback input and connect it to FBK pin. The
input-to-output skew is less than 250 ps and output-to-output
skew is less than 200 ps.
■
The CY2308-1 is the base part where the output frequencies
equal the reference if there is no counter in the feedback path.
The CY2308-1H is the high drive version of the -1 and rise and
fall times on this device are much faster.
The CY2308-2 enables the user to obtain 2x and 1x frequencies
on each output bank. The exact configuration and output
frequencies depend on the user’s selection of output that drives
the feedback pin.
The CY2308-3 enables the user to obtain 4x and 2x frequencies
on the outputs.
The CY2308-4 enables the user to obtain 2x clocks on all
outputs. Thus, the part is extremely versatile and is used in a
variety of applications.
The CY2308-5H is a high drive version with REF/2 on both
banks.
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For a complete list of related documentation, click
here.
Logic Block Diagram
/2
REF
PLL
MUX
FBK
CLKA1
CLKA2
CLKA3
CLKA4
/2
Extra Divider (–3, –4)
Extra Divider (–5H)
S2
S1
Select Input
Decoding
/2
CLKB1
CLKB2
CLKB3
Extra Divider (–2, –3)
CLKB4
Cypress Semiconductor Corporation
Document Number: 38-07146 Rev. *T
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 7, 2017
CY2308
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Select Input Decoding ...................................................... 3
Available CY2308 Configurations ................................... 4
Zero Delay and Skew Control .......................................... 4
Maximum Ratings ............................................................. 5
Operating Conditions ....................................................... 5
Electrical Characteristics ................................................. 5
Operating Conditions ....................................................... 6
Electrical Characteristics ................................................. 6
Thermal Resistance .......................................................... 6
Switching Characteristics ................................................ 7
Switching Characteristics ................................................ 8
Switching Waveforms ...................................................... 9
Typical Duty Cycle and IDD Trends .............................. 10
Typical Duty Cycle and IDD Trends .............................. 11
Test Circuits .................................................................... 12
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 14
Package Diagrams .......................................................... 15
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Errata ............................................................................... 17
Part Numbers Affected .............................................. 17
CY2308 Errata Summary .......................................... 17
CY2308 Qualification Status ..................................... 17
Document History Page ................................................. 19
Sales, Solutions, and Legal Information ...................... 21
Worldwide Sales and Design Support ....................... 21
Products .................................................................... 21
PSoC®Solutions ....................................................... 21
Cypress Developer Community ................................. 21
Technical Support ............................................................. 21
Document Number: 38-07146 Rev. *T
Page 2 of 21
CY2308
Pinouts
Figure 1. 16-pin SOIC pinout (Top View)
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FBK
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
Pin Definitions
16-pin SOIC
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Signal
REF
[1]
CLKA1
[2]
CLKA2
[2]
V
DD
GND
CLKB1
[2]
CLKB2
[2]
S2
[3]
S1
[3]
CLKB3
[2]
CLKB4
[2]
GND
V
DD
CLKA3
[2]
CLKA4
[2]
FBK
Input reference frequency
Clock output, Bank A
Clock output, Bank A
Power supply voltage
Power supply ground
Clock output, Bank B
Clock output, Bank B
Select input, bit 2
Select input, bit 1
Clock output, Bank B
Clock output, Bank B
Power supply ground
Power supply voltage
Clock output, Bank A
Clock output, Bank A
PLL feedback input
Description
Select Input Decoding
S2
0
0
1
1
S1
0
1
0
1
CLOCK A1–A4
Tri-state
Driven
Driven
[4]
Driven
CLOCK B1–B4
Tri-state
Tri-state
Driven
[4]
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shutdown
Y
N
Y
N
Notes
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
4. Outputs inverted and PLL bypass mode for 2308-2 and 2308-3, S2 = 1 and S1 = 0.
Document Number: 38-07146 Rev. *T
Page 3 of 21
CY2308
Available CY2308 Configurations
Device
CY2308-1
CY2308-1H
CY2308-2
CY2308-2
CY2308-3
CY2308-3
CY2308-4
CY2308-5H
Feedback From
[5]
Bank A or Bank B
Bank A or Bank B
Bank A
Bank B
Bank A
Bank B
Bank A or Bank B
Bank A or Bank B
Bank A Frequency
Reference
Reference
Reference
2 × Reference
2 × Reference
4 × Reference
2 × Reference
Reference / 2
Bank B Frequency
Reference
Reference
Reference / 2
Reference
Reference
[6]
2 × Reference
2 × Reference
Reference / 2
Zero Delay and Skew Control
Figure 2. REF. Input to CLKA/CLKB Delay Versus Difference in Loading between FBK Pin and CLKA/CLKB Pins
To close the feedback loop of the CY2308, the user has to
connect any one of the eight available output pins to FBK pin.
The output driving the FBK pin drives a total load of 7 pF plus
any additional load that it drives. The relative loading of this
output to the remaining outputs adjusts the input-output delay as
shown in the
Figure 2.
For applications requiring zero input-output delay, all outputs
including the one providing feedback is equally loaded.
If input-output delay adjustments are required, use the
Zero
Delay and Skew Control
graph to calculate loading differences
between the feedback output and remaining outputs.
For zero output-output skew, outputs are loaded equally. For
further information on using CY2308, refer to the application note
AN1234 - Understanding Cypress’s Zero Delay Buffers.
Notes
5. User has to select one of the available outputs that drive the feedback pin and need to connect selected output pin to FBK pin externally.
6. Output phase is indeterminant (0 ° or 180 ° from input clock). If phase integrity is required, use CY2308-2.
Document Number: 38-07146 Rev. *T
Page 4 of 21
CY2308
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Supply voltage to ground potential ..............–0.5 V to +7.0 V
DC input voltage (except REF) ........... –0.5 V to V
DD
+ 0.5 V
DC input voltage REF .......................................–0.5 V to 7 V
Storage temperature ................................ –65 °C to +150 °C
Junction temperature ................................................. 150 °C
Static discharge voltage
(MIL-STD-883, Method 3015) .................................. >2000 V
Operating Conditions
For Commercial Temperature Devices
Parameter
V
DD
T
A
C
L
C
IN
t
PU
Supply voltage
Operating temperature (ambient temperature)
Load capacitance, below 100 MHz
Load capacitance, from 100 MHz to 133 MHz
Input capacitance
[7]
Power up time for all V
DD
’s to reach minimum specified voltage (power ramps must
be monotonic)
Description
Min
3.0
0
–
–
–
0.05
Max
3.6
70
30
15
7
50
Unit
V
°C
pF
pF
pF
ms
Electrical Characteristics
For Commercial Temperature Devices
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
Description
Input LOW voltage
Input HIGH voltage
Input LOW current
Input HIGH current
Output LOW voltage
[8]
Output HIGH voltage
[8]
V
IN
= 0 V
V
IN
= V
DD
I
OL
= 8 mA (-1, -2, -3, -4)
I
OL
= 12 mA (-1H, -5H)
I
OH
= –8 mA (-1, -2, -3, -4)
I
OH
= –12 mA (-1H, -5H)
REF = 0 MHz
Unloaded outputs, 100 MHz REF, select inputs at
V
DD
or GND
Unloaded outputs, 66 MHz REF (-1, -2, -3, -4)
Unloaded outputs, 33 MHz REF (-1, -2, -3, -4)
Test Conditions
Min
–
2.0
–
–
–
2.4
–
–
–
–
–
Max
0.8
–
50.0
100.0
0.4
–
12.0
45.0
70.0
(-1H, -5H)
32.0
18.0
Unit
V
V
A
A
V
V
A
mA
mA
mA
mA
I
DD
(PD mode) Power down supply current
I
DD
Supply current
Notes
7. Applies to both Ref clock and FBK.
8. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number: 38-07146 Rev. *T
Page 5 of 21
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