CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Analog Specifications
SYMBOL
R
TOTAL
R
W
C
H
/C
L
/C
W
I
LkgDCP
INL (Note 7)
DNL (Note 6)
Over recommended operating conditions unless otherwise stated.
PARAMETER
TEST CONDITIONS
W, U versions respectively
-20
V
CC
= 3.3V @ +25°C
Wiper current = V
CC
/R
TOTAL
70
10/10/25
Voltage at pin from GND to V
CC
-1
Monotonic over all tap positions
W option -0.75
U option
-0.5
0
0
-7
-2
1
0.5
-1
-0.5
±4
0.1
1
MIN
TYP
(Notes 2)
10, 50
+20
200
MAX
UNIT
kΩ
%
Ω
pF
µA
R
H
to R
L
Resistance
R
H
to R
L
Resistance Tolerance
Wiper resistance
Potentiometer Capacitance
(Note 14, Equivalent circuitry)
Leakage on DCP pins (Note 14)
VOLTAGE DIVIDER MODE
(0V @ RL; V
CC
@ RH; measured at RW, unloaded)
Integral Non-Linearity
Differential Non-Linearity
1
+0.75
+0.5
7
2
0
0
ppm/°C
LSB (Note 3)
LSB (Note 3)
LSB (Note 3)
LSB (Note 3)
LSB (Note 3)
ZSerror (Note 4) Zero-Scale Error
W option
U option
FSerror (Note 5) Full-Scale Error
W option
U option
TC
V
(Notes 8, 14) Ratiometric Temperature Coefficient DCP Register set to 80 hex
RINL (Note 12)
RDNL (Note 6)
Integral Non-Linearity
Differential Non-Linearity
DCP register set between 20 hex and FF hex.
Monotonic over all tap positions
-1
RESISTOR MODE
(Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected)
1
+0.75
+0.5
1
0.5
±35
7
2
MI (Note 9)
MI (Note 9)
MI (Note 9)
MI (Note 9)
MI (Note 9)
ppm/°C
DCP register set between 20 hex W option -0.75
and FF hex. Monotonic over all tap
U option -0.5
positions
W option
U option
0
0
Roffset (Note 10) Offset
TC
R
(Notes 13, 14)
Resistance Temperature Coefficient DCP register set between 20 hex and FF hex
3
FN8234.2
November 10, 2006
ISL90810
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
SYMBOL
I
CC1
I
SB
PARAMETER
V
CC
Supply Current
(Volatile Write/Read)
V
CC
Current (Standby)
TEST CONDITIONS
f
SCL
= 400kHz; SDA = Open; (for I
2
C, Active,
Read and Volatile Write States only)
V
CC
= +5.5V, I
2
C Interface in Standby State,
Temperature range from -40°C to +85°C
V
CC
= +5.5V, I
2
C Interface in Standby State,
Temperature range from -40°C to +105°C
V
CC
= +3.6V, I
2
C Interface in Standby State,
Temperature range from -40°C to +85°C
V
CC
= +3.6V, I
2
C Interface in Standby State,
Temperature range from -40°C to +105°C
I
LkgDig
Leakage Current at Pins SDA and
SCL
Voltage at pin from GND to V
CC
SCL falling edge of last bit of DCP Data Byte to
wiper change
Minimum V
CC
at which memory recall occurs
1.8
0.2
V
CC
above Vpor, to DCP Initial Value Register
recall completed, and I
2
C Interface in standby state
3
-10
MIN
TYP
(Note 1)
20
2
2
0.8
0.8
MAX
100
5
8
2
5
10
1
2.6
UNITS
µA
µA
µA
µA
µA
µA
µs
V
V/ms
ms
t
DCP
(Note 14) DCP Wiper Response Time
Vpor
V
CC
Ramp
t
D
(Note 14)
Power-On Recall Voltage
V
CC
Ramp Rate
Power-Up Delay
SERIAL INTERFACE SPECIFICATIONS
V
IL
V
IH
Hysteresis
(Note 14)
SDA, and SCL Input Buffer LOW
Voltage
SDA, and SCL Input Buffer HIGH
Voltage
SDA and SCL Input Buffer Hysteresis
-0.3
0.7*V
CC
0.05*
V
CC
0
0.4
10
400
Any pulse narrower than the max spec is
suppressed.
50
900
1300
0.3*V
CC
V
CC
+0.3
V
V
V
V
pF
kHz
ns
ns
ns
V
OL
(Note 14) SDA Output Buffer LOW Voltage,
Sinking 4mA
Cpin (Note 14) SDA, and SCL Pin Capacitance
f
SCL
t
IN
(Note 14)
t
AA
(Note 14)
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of V
CC
, until SDA
Valid
exits the 30% to 70% of V
CC
window.
t
BUF
(Note 14) Time the Bus Must be Free Before the SDA crossing 70% of V
CC
during a STOP
Start of a New Transmission
condition, to SDA crossing 70% of V
CC
during
the following START condition.
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
Input Data Setup Time
Input Data Hold Time
STOP Condition Setup Time
Measured at the 30% of V
CC
crossing.
Measured at the 70% of V
CC
crossing.
SCL rising edge to SDA falling edge. Both
crossing 70% of V
CC
.
From SDA falling edge crossing 30% of V
CC
to
SCL falling edge crossing 70% of V
CC
.
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of V
CC
From SCL rising edge crossing 70% of V
CC
to
SDA entering the 30% to 70% of V
CC
window.
From SCL rising edge crossing 70% of V
CC
, to
SDA rising edge crossing 30% of V
CC
.
1300
600
600
600
100
0
600
ns
ns
ns
ns
ns
ns
ns
4
FN8234.2
November 10, 2006
ISL90810
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
(Continued)
SYMBOL
t
HD:STO
t
DH
(Note 14)
t
R
(Note 14)
t
F
(Note 14)
Cb (Note 14)
PARAMETER
TEST CONDITIONS
MIN
600
0
20 +
0.1 * Cb
20 +
0.1 * Cb
10
1
250
250
400
TYP
(Note 1)
MAX
UNITS
ns
ns
ns
ns
pF
kΩ
STOP Condition Hold Time for Read, From SDA rising edge to SCL falling edge. Both
or Volatile Only Write
crossing 70% of V
CC
.
Output Data Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive Loading of SDA or SCL
From SCL falling edge crossing 30% of V
CC
, until
SDA enters the 30% to 70% of V
CC
window.
From 30% to 70% of V
CC
From 70% to 30% of V
CC
Total on-chip and off-chip
Maximum is determined by t
R
and t
F
.
For Cb = 400pF, max is about 2~2.5kΩ.
For Cb = 40pF, max is about 15~20kΩ
Rpu (Note 14) SDA and SCL Bus Pull-Up Resistor
Off-Chip
SDA vs SCL Timing
t
F
t
HIGH
t
LOW
t
R
SCL
t
SU:STA
t
HD:STA
SDA
(INPUT TIMING)
t
SU:DAT
t
HD:DAT
t
SU:STO
t
AA
SDA
(OUTPUT TIMING)
t
DH
t
BUF
NOTES:
2. Typical values are for T
A
= +25°C and 3.3V supply voltage.
3. LSB: [V(RW)
255
– V(RW)
0
]/255. V(RW)
255
and V(RW)
0
are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
4. ZS error = V(RW)
0
/LSB.
5. FS error = [V(RW)
255
– V
CC
]/LSB.
6. DNL = [V(RW)
i
– V(RW)
i-1
]/LSB-1, for i = 1 to 255. i is the DCP register setting.
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