Intel
®
C600 Series Chipset and
Intel
®
X79 Express Chipset
Datasheet
April 2013
Document Number:
326514-002
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®
C600 Series Chipset described in this document may contain design defects or errors known as errata which may cause
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Intel
®
Active Management Technology requires the computer system to have an Intel(R) AMT-enabled chipset, network hardware
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®
Trusted Execution Technology (Intel
®
TXT) requires
a computer system with Intel
®
Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code
Modules and an Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor,
an OS or an application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing
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Intel
®
High Definition Audio requires a system with an appropriate Intel chipset and a motherboard with an appropriate codec and
the necessary drivers installed. System sound quality will vary depending on actual implementation, controller, codec, drivers and
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®
HD audio, refer to http://www.intel.com/.
Intel
®
Virtualization Technology requires a computer system with an enabled Intel
®
processor, BIOS, virtual machine monitor
(VMM) and, for some uses, certain computer system software enabled for it. Functionality, performance or other benefits will vary
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*Other names and brands may be claimed as the property of others.
Copyright © 2013, Intel Corporation
2
Intel® C600 Series Chipset and Intel® X79 Express Chipset
Datasheet
Contents
1
Introduction
............................................................................................................ 41
1.1
About This Manual ............................................................................................. 41
1.2
Overview ......................................................................................................... 44
1.2.1 Capability Overview ................................................................................ 45
1.3
Intel
®
C600 Series Chipset and Intel
®
X79 Express Chipset SKU Definition ............... 50
Signal Description
................................................................................................... 51
2.1
Direct Media Interface (DMI) to Host Controller ..................................................... 53
2.2
PCI Express* .................................................................................................... 53
2.3
PCI Express* Uplink (Intel
®
C606, C608 Chipset SKUs Only)................................... 54
2.4
PCI Interface .................................................................................................... 54
2.5
Serial ATA Interface........................................................................................... 56
2.6
SAS Interface (SRV/WS SKUs Only) ..................................................................... 58
2.7
LPC Interface.................................................................................................... 60
2.8
Interrupt Interface ............................................................................................ 60
2.9
USB 2.0 Interface.............................................................................................. 61
2.10 Power Management Interface.............................................................................. 62
2.11 Processor Interface............................................................................................ 64
2.12 SMBus Interface................................................................................................ 65
2.13 System Management Interface............................................................................ 65
2.14 SAS System Management Interface (SRV/WS SKUs Only)....................................... 65
2.15 Real Time Clock Interface ................................................................................... 66
2.16 Miscellaneous Signals ........................................................................................ 66
2.17 Intel
®
High Definition Audio (Intel
®
HD Audio) Link ............................................... 67
2.18 Serial Peripheral Interface (SPI) .......................................................................... 68
2.19 Thermal Signals ................................................................................................ 68
2.20 JTAG Signals .................................................................................................... 68
2.21 Clock Signals .................................................................................................... 69
2.22 General Purpose I/O Signals ............................................................................... 70
2.23 GPIO Serial Expander Signals.............................................................................. 73
2.24 Manageability Signals ........................................................................................ 73
2.25 Power and Ground Signals .................................................................................. 74
2.26 Pin Straps ........................................................................................................ 76
2.26.1 Functional Straps ................................................................................... 76
2.27 External RTC Circuitry ........................................................................................ 79
PCH Pin States.........................................................................................................
81
3.1
Integrated Pull-Ups and Pull-Downs ..................................................................... 81
3.2
Output and I/O Signals Planes and States............................................................. 82
3.3
Power Planes for Input Signals ............................................................................ 87
System Clock Domains.............................................................................................
91
4.1
System Clock Domains....................................................................................... 91
4.2
Functional Blocks .............................................................................................. 93
Functional Description
............................................................................................. 95
5.1
PCI-to-PCI Bridge (D30:F0) ................................................................................ 95
5.1.1 PCI Bus Interface ................................................................................... 95
5.1.2 PCI Bridge As an Initiator ........................................................................ 95
5.1.3 Parity Error Detection and Generation ....................................................... 97
5.1.4 PCIRST# ............................................................................................... 98
5.1.5 Peer Cycles ........................................................................................... 98
5.1.6 PCI-to-PCI Bridge Model.......................................................................... 98
5.1.7 IDSEL to Device Number Mapping ............................................................ 99
2
3
4
5
Intel® C600 Series Chipset and Intel® X79 Express Chipset
Datasheet
3
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.1.8 Standard PCI Bus Configuration Mechanism................................................99
PCI Legacy Mode ...............................................................................................99
PCI Express*................................................................................................... 100
5.3.1 PCI Express* UpLink Port (Bn:D0:F0) (SRV/WS SKUs Only) ....................... 100
5.3.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7) .......................... 106
Gigabit Ethernet Controller (B0:D25:F0) ............................................................. 110
5.4.1 GbE PCI Express Bus Interface ............................................................... 112
5.4.2 Error Events and Error Reporting ............................................................ 113
5.4.3 Ethernet Interface ................................................................................ 113
5.4.4 PCI Power Management ......................................................................... 113
5.4.5 Configurable LEDs................................................................................. 115
5.4.6 Function Level Reset Support (FLR) (SRV/WS SKUs Only) .......................... 116
LPC Bridge (with System and Management Functions) (D31:F0)............................. 117
5.5.1 LPC Interface ....................................................................................... 117
DMA Operation (D31:F0) .................................................................................. 121
5.6.1 Channel Priority.................................................................................... 122
5.6.2 Address Compatibility Mode ................................................................... 122
5.6.3 Summary of DMA Transfer Sizes ............................................................. 122
5.6.4 Autoinitialize ........................................................................................ 123
5.6.5 Software Commands ............................................................................. 123
LPC DMA ........................................................................................................ 124
5.7.1 Asserting DMA Requests ........................................................................ 124
5.7.2 Abandoning DMA Requests..................................................................... 124
5.7.3 General Flow of DMA Transfers ............................................................... 125
5.7.4 Terminal Count..................................................................................... 125
5.7.5 Verify Mode ......................................................................................... 125
5.7.6 DMA Request Deassertion ...................................................................... 126
5.7.7 SYNC Field / LDRQ# Rules ..................................................................... 126
8254 Timers (D31:F0) ...................................................................................... 127
5.8.1 Timer Programming .............................................................................. 127
5.8.2 Reading from the Interval Timer ............................................................. 128
8259 Interrupt Controllers (PIC) (D31:F0)........................................................... 130
5.9.1 Interrupt Handling ................................................................................ 131
5.9.2 Initialization Command Words (ICWx) ..................................................... 132
5.9.3 Operation Command Words (OCW) ......................................................... 133
5.9.4 Modes of Operation ............................................................................... 133
5.9.5 Masking Interrupts................................................................................ 135
5.9.6 Steering PCI Interrupts.......................................................................... 135
Advanced Programmable Interrupt Controller (APIC) (D31:F0)............................... 136
5.10.1 Interrupt Handling ................................................................................ 136
5.10.2 Interrupt Mapping................................................................................. 136
5.10.3 PCI / PCI Express* Message-Based Interrupts .......................................... 137
5.10.4 IOxAPIC Address Remapping (SRV/WS SKUs Only) ................................... 137
5.10.5 External Interrupt Controller Support ...................................................... 137
Serial Interrupt (D31:F0) .................................................................................. 138
5.11.1 Start Frame ......................................................................................... 138
5.11.2 Data Frames ........................................................................................ 139
5.11.3 Stop Frame.......................................................................................... 139
5.11.4 Specific Interrupts Not Supported using SERIRQ ....................................... 139
5.11.5 Data Frame Format............................................................................... 140
Real Time Clock (D31:F0) ................................................................................. 140
5.12.1 Update Cycles ...................................................................................... 141
5.12.2 Interrupts ............................................................................................ 141
5.12.3 Lockable RAM Ranges............................................................................ 141
5.12.4 Century Rollover................................................................................... 142
5.12.5 Clearing Battery-Backed RTC RAM........................................................... 142
4
Intel® C600 Series Chipset and Intel® X79 Express Chipset
Datasheet
5.13
5.14
5.15
5.16
5.17
5.18
5.19
Processor Interface (D31:F0) ............................................................................ 143
5.13.1 Processor Interface Signals and VLW Messages ........................................ 144
5.13.2 Dual-Processor Issues........................................................................... 145
5.13.3 Virtual Legacy Wire (VLW) Messages....................................................... 145
Power Management ......................................................................................... 146
5.14.1 Features ............................................................................................. 146
5.14.2 PCH and System Power States ............................................................... 146
5.14.3 System Power Planes ............................................................................ 148
5.14.4 SMI#/SCI Generation ........................................................................... 148
5.14.5 C-States ............................................................................................. 151
5.14.6 Sleep States ........................................................................................ 151
5.14.7 Event Input Signals and Their Usage....................................................... 155
5.14.8 ALT Access Mode.................................................................................. 158
5.14.9 System Power Supplies, Planes, and Signals ............................................ 161
5.14.10Legacy Power Management Theory of Operation ....................................... 163
5.14.11Reset Behavior..................................................................................... 163
System Management (D31:F0).......................................................................... 165
5.15.1 Theory of Operation.............................................................................. 166
5.15.2 TCO Modes .......................................................................................... 167
General Purpose I/O (D31:F0) .......................................................................... 169
5.16.1 Power Wells......................................................................................... 169
5.16.2 SMI# SCI and NMI Routing.................................................................... 169
5.16.3 Triggering ........................................................................................... 169
5.16.4 GPIO Registers Lockdown ...................................................................... 169
5.16.5 Serial POST Codes over GPIO................................................................. 170
5.16.6 GPIO Serial Expander (GSX) .................................................................. 172
SATA Host Controller (D31:F2, F5) .................................................................... 174
5.17.1 SATA 6 Gb/s Support ............................................................................ 174
5.17.2 SATA Feature Support........................................................................... 174
5.17.3 Theory of Operation.............................................................................. 175
5.17.4 SATA Swap Bay Support ....................................................................... 176
5.17.5 Hot-Plug Operation ............................................................................... 176
5.17.6 Function Level Reset Support (FLR) (SRV/WS SKUs Only) .......................... 176
5.17.7 Intel
®
Rapid Storage Technology Enterprise Configuration ......................... 177
5.17.8 Power Management Operation................................................................ 178
5.17.9 SATA Device Presence........................................................................... 179
5.17.10SATA LED............................................................................................ 180
5.17.11AHCI Operation.................................................................................... 180
5.17.12SGPIO Signals ..................................................................................... 181
5.17.13External SATA...................................................................................... 184
SAS/SATA Controller Overview (SAS is for SRV/WS SKUs Only) ............................. 185
5.18.1 SCU Features....................................................................................... 185
5.18.2 SCU Configurations............................................................................... 186
5.18.3 Storage Controller Unit (SCU) Architecture .............................................. 188
5.18.4 SCU Physical Layer/PHY Overview .......................................................... 196
5.18.5 Interrupts and Interrupt Coalescing ........................................................ 198
5.18.6 SMU Error and Event Generation ............................................................ 199
5.18.7 Host Interface Error Conditions .............................................................. 200
5.18.8 Host Interface Messages Received .......................................................... 204
5.18.9 Reset.................................................................................................. 204
5.18.10SGPIO ................................................................................................ 205
High Precision Event Timers (HPET) ................................................................... 214
5.19.1 Timer Accuracy .................................................................................... 214
5.19.2 Interrupt Mapping ................................................................................ 215
5.19.3 Periodic versus Non-Periodic Modes ........................................................ 216
5.19.4 Enabling the Timers.............................................................................. 217
Intel® C600 Series Chipset and Intel® X79 Express Chipset
Datasheet
5
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