LNBS21
LNB SUPPLY AND CONTROL IC WITH
STEP-UP CONVERTER AND I
2
C INTERFACE
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DESCRIPTION
Intended for analog and digital satellite STB
receivers/SatTV, sets/PC cards, the LNBS21 is a
monolithic voltage regulator and interface IC,
Figure 1: Schematic Diagram
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PowerSO-20
COMPLETE INTERFACE BETWEEN LNB
AND I
2
C
TM
BUS
BUILT-IN DC/DC CONTROLLER FOR
SINGLE 12V SUPPLY OPERATION
ACCURATE BUILT-IN 22KHz TONE
OSCILLATOR
SUITS WIDELY ACCEPTED STANDARDS
FAST OSCILLATOR START-UP FACILITATES
DiSEqC
TM
ENCODING
BUILT-IN 22KHz TONE DETECTOR
SUPPORTS BI-DIRECTIONAL DiSEqC
TM
LOOP-THROUGH FUNCTION FOR SLAVE
OPERATION
LNB SHORT CIRCUIT PROTECTION AND
DIAGNOSTIC
CABLE LENGTH DIGITAL COMPENSATION
INTERNAL OVER TEMPERATURE
PROTECTION
assembled in PowerSO-20, specifically designed
to provide the power and the 13/18V, 22KHz tone
signalling to the LNB downconverter in the
antenna or to the multiswitch box. In this
application field, it offers a complete solution with
extremely low component count, low power
dissipation together with simple design and I
2
C
TM
standard interfacing.
This IC has a built in DC/DC step-up controller
that, from a single supply source ranging from 8 to
15V, generates the voltages that let the linear
LNBS21
Feedback
LT1
Sense
Step-up
Controller
LT2
Vup
OUT
Vcc
Preregul.+
U.V.lockout
Enable
Byp
+P.ON res.
I Select
V Select
Linear Post-reg
+Modulator
+Protections
EXTM
SDA
SCL
ADDR
DSQIN
I²C
interf.
22KHz
Oscill.
Diagnostics
DETIN
Tone
Detector
DSQOUT
October 2004
Rev. 3
1/21
LNBS21
post-regulator to work at a minimum dissipated
power. An UnderVoltage Lockout circuit will
disable the whole circuit when the supplied V
CC
drops below a fixed threshold (6.7V typically). The
internal 22KHz tone generator is factory trimmed
in accordance to the standards, and can be
controlled either by the I
2
C
TM
interface or by a
dedicated pin (DSQIN) that allows immediate
DiSEqC
TM
data encoding (*). All the functions of
this IC are controlled via I
2
C
TM
bus by writing 6
bits on the System Register (SR, 8 bits). The
same register can be read back, and two bits will
report the diagnostic status. When the IC is put in
Stand-by (EN bit LOW), the power blocks are
disabled and the loop-through switch between
LT1 and LT2 pins is closed, thus leaving all LNB
powering and control functions to the Master
Receiver (**). When the regulator blocks are
active (EN bit HIGH), the output can be logic
controlled to be 13 or 18 V (typ.) by mean of the
VSEL bit (Voltage SELect) for remote controlling
of non-DiSEqC LNBs. Additionally, it is possible to
increment by 1V (typ.) the selected voltage value
to compensate for the excess voltage drop along
the coaxial cable (LLC bit HIGH). In order to
minimize the power dissipation, the output voltage
of the internal step-up converter is adjusted to
allow the linear regulator to work at minimum
dropout. Another bit of the SR is addressed to the
remote control of non-DiSEqC LNBs: the TEN
(Tone ENable) bit. When it is set to HIGH, a
continuous 22KHz tone is generated regardless of
the DSQIN pin logic status. The TEN bit must be
set LOW when the DSQIN pin is used for
DiSEqC
TM
encoding. The fully bi-directional
DiSEqC
TM
interfacing is completed by the built-in
22KHz tone detector. Its input pin (DETIN) must
be AC coupled to the DiSEqC
TM
bus, and the
extracted PWK data are available on the
DSQOUT pin (*).
In order to improve design flexibility and to allow
implementation of newcoming LNB remote control
standards, an analogic modulation input pin is
available (EXTM). An appropriate DC blocking
capacitor must be used to couple the modulating
signal source to the EXTM pin. When external
modulation is not used, the relevant pin can be left
open.
The current limitation block has two thresholds
that can be selected by the I
SEL
bit of the SR; the
lower threshold is between 650 and 900mA
(I
SEL
=HIGH), while the higher threshold is
between 750 and 1000mA (I
SEL
=LOW).
The current protection block is SOA type. This
limits the short circuit current (I
SC
) typically at
300mA with I
SEL
=HIGH and at 400mA with
I
SEL
=LOW when the output port is connected to
ground.
It is possible to set the Short Circuit Current
protection either statically (simple current clamp)
or dynamically by the PCL bit of the SR; when the
PCL (Pulsed Current Limiting) bit is set to LOW,
the
overcurrent
protection
circuit
works
dynamically: as soon as an overload is detected,
the output is shut-down for a time t
off
, typically
900ms. Simultaneously the OLF bit of the System
Register is set to HIGH. After this time has
elapsed, the output is resumed for a time t
on
=1/
10t
off
(typ.). At the end of t
on
, if the overload is still
detected, the protection circuit will cycle again
through T
off
and T
on
. At the end of a full Ton in
which no overload is detected, normal operation is
resumed and the OLF bit is reset to LOW. Typical
T
on
+T
off
time is 990ms and it is determined by an
internal timer. This dynamic operation can greatly
reduce the power dissipation in short circuit
condition, still ensuring excellent power-on start
up in most conditions (**).
However, there could be some cases in which an
highly capacitive load on the output may cause a
difficult start-up when the dynamic protection is
chosen. This can be solved by initiating any power
start-up in static mode (PCL=HIGH) and then
switching to the dynamic mode (PCL=LOW) after
a chosen amount of time. When in static mode,
the OLF bit goes HIGH when the current clamp
limit is reached and returns LOW when the
overload condition is cleared.
This IC is also protected against overheating:
when the junction temperature exceeds 150°C
(typ.), the step-up converter and the linear
regulator are shut off, the loop-trough switch is
opened, and the OTF bit of the SR is set to HIGH.
Normal operation is resumed and the OTF bit is
reset to LOW when the junction is cooled down to
140°C (typ.).
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(*): External components are needed to comply to bi-directional DiSEqC
TM
bus hardware requirements. Full compliance of the whole appli-
cation to DiSEqC
TM
specifications is not implied by the use of this IC.
(**): The current limitation circuit has no effect on the loop-through switch. When EN bit is LOW, the current flowing from LT1 to LT2 must be
externally limited.
2/21
LNBS21
Table 1: Ordering Codes
TYPE
LNBS21
PowerSO-20
(Tube)
LNBS21PD
PowerSO-20
(Tape & Reel)
LNBS21PD-TR
Table 2: Absolute Maximum Ratings
Symbol
V
CC
V
UP
I
O
DC Input Voltage
DC Input Voltage
Output Current
Parameter
Value
16
25
20
Internally Limited
-0.3 to 22
-0.3 to 7
2
7
Unit
V
V
V
mA
V
V
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.
Table 3: Thermal Data
Symbol
R
thj-case
Figure 2: Pin Connection
(top view)
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V
O
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I
DC Output Pin Voltage
Logic Input Voltage (SDA, SCL, DSQIN)
Detector Input Signal Amplitude
Bypass Switch ON Current
Gate Current
Logic High Output Voltage (DSQOUT)
Bypass Switch OFF Voltage
Current Sense Voltage
V
DETIN
V
OH
I
LT
V
LT
V
PP
V
mA
V
900
±20
I
GATE
±400
mA
V
V
V
SENSE
T
stg
T
op
-0.3 to 1
-0.3 to 7
V
ADDRESS
Address Pin Voltage
Storage Temperature Range
-40 to +150
-40 to +125
°C
°C
Operating Junction Temperature Range
Parameter
PowerSO-20
2
Unit
Thermal Resistance Junction-case
°C/W
V
LT1
, V
LT2
DC Input Voltage
PowerSO-20
3/21
LNBS21
Table 4: Pin Description
SYMBOL
V
CC
NAME
Supply Input
FUNCTION
8V to 15V supply. A 220µF bypass capacitor to
GND with a 470nF (ceramic) in parallel is
recommended
External MOS switch Gate connection of the
step-up converter
Current Sense comparator input. Connected to
current sensing resistor
Input of the linear post-regulator. The voltage on this
pin is monitored by internal step-ut controller to
keep a minimum dropout across the linear pass
transistor
Output of the linear post regulator modulator to the
LNB. See truth table for voltage selections.
Bidirectional data from/to I
2
C bus.
PIN NUMBER
vs. PACKAGE
18
GATE
SENSE
V
up
External Switch Gate
Current Sense Input
Step-up Voltage
17
16
19
DSQOUT DiSEqC Output
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OUT
SDA
SCL
Output Port
Serial Data
2
12
Serial Clock
DSQIN
DiSEqC Input
DETIN
Detector In
EXTM
GND
BYP
LT1
External Modulator
Ground
Bypass Capacitor
Loop Through Switch
LT2
ADDR
Loop Through Switch
Address Setting
Clock from I
2
C bus.
When the TEN bit of the System Register is LOW,
this pin will accept the DiSEqC code from the main
µcontroller.
The LNBS21 will use this code to
modulate the internally generated 22kHz carrier. Set
to GND the pin if not used.
22kHz Tone Detector Input. Must be AC coupled to
the DiSEqC bus.
Open collector output of the tone Detector to the
main
µcontroller
for DiSEqC data decoding. It is
LOW when tone is detected.
External Modulation Input. Need DC decoupling to
the AC source. If not used, can be left open.
Pins to be connected to ground.
Needed for internal preregulator filtering
In standby mode the power switch between LT1 and
LT2 is closed. Max allowed current is 900mA. this
pin can be left open if loop through function is not
needed.
Same as above
Four I
2
C bus addresses available by setting the
Address Pin level voltage
13
14
9
15
5
1, 6, 10, 11, 20
8
4
3
7
4/21
LNBS21
Figure 3: Typical Application Circuit
D1 1N4001
IC1
Master STB
Vup
C2
220µF
C3
470nF
Ceramic
LT1
C7
10nF
IC2
(Note 3)
STS4DNFS30L
LT2
270µH
Gate
Vo
C8
10nF
D2
BAT43
to LNB
(*) Set to GND if not used
(**) filter to be used according to EUTELSAT recommendation to implement the DiSEqC
TM
2.x, not needed if bidirectional DiSEqC
TM
2.x is
not implemented (see DiSEqC implementation note)
(***) IC2 is a ST Fettky, STS4DNFS30L, that includes both the schottky diode and the N-Channel MosFet, needed for the DC/DC converter,
in a So-8 package. It can be replaced by a schottky diode (STPS2L3A or similar) and a N-Channel MosFet (STN4NF03L or similar)
I
2
C BUS INTERFACE
Data transmission from main µP to the LNBS21
and viceversa takes place through the 2 wires I
2
C
bus interface, consisting of the two lines SDA and
SCL (pull-up resistors to positive supply voltage
must be externally connected).
DATA VALIDITY
As shown in fig. 1, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
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LNBS21
15 ohm
see Note 2
L1=22µH
Sense
R
sc
DETIN
(Note 1)
Byp
0.1Ω
Ω
(Note 4)
C6
10nF
Vcc
C5
470nF
Vin
12V
C1
220µF
C4
470nF
Ceramic
DSQIN(Note 1)
SCL
EXTM
ADDRESS
DSQOUT
0<Vaddr<V
Byp
SDA
GND
Every byte transferred to the SDA line must
contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
START AND STOP CONDITIONS
As shown in fig.2 a start condition is a HIGH to
LOW transition of the SDA line while SCL is HIGH.
The stop condition is a LOW to HIGH transition of
the SDA line while SCL is HIGH. A STOP
conditions must be sent before each START
condition.
BYTE FORMAT
ACKNOWLEDGE
The master (µP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 3). The peripheral (LNBS21) that
acknowledges has to pull-down (LOW) the SDA
line during the acknowledge clock pulse, so that
the SDA line is stable LOW during this clock pulse.
The peripheral which has been addressed has to
generate an acknowledge after the reception of
each byte, otherwise the SDA line remains at the
HIGH level during the ninth clock pulse time. In
this case the master transmitter can generate the
STOP information in order to abort the transfer.
The LNBS21 won't generate the acknowledge if
the V
CC
supply is below the Undervoltage Lockout
threshold (6.7V typ.).
TRANSMISSION WITHOUT ACKNOWLEDGE
Avoiding to detect the acknowledge of the
LNBS21, the µP can use a simpler transmission:
5/21
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