PRELIMINARY
CM4072
Low Noise Charge Pump/Linear Regulator LED Driver
Features
•
•
•
•
•
•
•
•
•
•
Low noise regulator with integrated charge pump
voltage-booster
5V output with input voltage as low as 2.8V
Charge pump can also power an external LDO
Low noise in 20Hz to 20kHz audio band
Up to 200mA continuous output current
Low operating and shutdown currents
Stable with low-ESR ceramic or tantalum capaci-
tors
Over-current and over-temperature protection
10-lead TDFN package, 3mm x 3mm
Lead-free versions available
Product Description
The CM4072 Low-noise Charge Pump / LDO Regulator is
designed to power white backlight LEDs used in main dis-
plays or camera flash LEDs in wireless handsets. The 5V
output provides up to 100mA continuous current for input
voltages from 3.0V to 5.5V, and up to 200mA for a nar-
rower range. This is accomplished with an integrated
charge pump that boosts the input voltage before feeding
it to an internal LDO linear regulator. The CM4072 oper-
ates with excellent power supply ripple rejection while
maintaining good power efficiency. The device utilizes two
external capacitors and operates at 250kHz. Separate
analog and digital ground pins are provided for the charge
pump and the rest of the circuitry to eliminate ground
noise feed-through from the charge pump to the regulated
output.
The CM4072 provides both overcurrent and thermal over-
load protection. Two enable inputs provide flexibility in
powering down the device. To maximize power saving in
shutdown mode, both enable inputs should be at a logic
low level. For applications that require the 5V output to be
re-established with minimum delay after shutdown, the
charge pump can be left enabled while the regulator is
disabled. The CMOS LDO regulator features low quies-
cent current even at full load, making it very suitable for
power sensitive applications.
A bypass pin is provided to further minimize noise by con-
necting an external capacitor between this pin and
ground.
The CM4072 is available in a 10-lead TDFN package,
with optional lead-free finishing, and is ideal for space crit-
ical applications
.
Applications
•
•
•
•
White backlight LEDs for main display in wireless
handsets and LCD modules
Power flash LEDs for camera phones
3.3V to 5V conversion in PCMCIA cards, PCI
Express Cards, other applications needing 5V
5V analog supply for audio codec in notebook
computers, PDAs, MP3 players, etc
Typical Application
Simplified Block Diagram
DGND
V
IN
1
CHARGE PUMP
10
2
9
3
CP-
C
P
CP+
1
V
IN
C
S
+
2.2μF
10
9
2
3
4
5
0.1μF*
*Optional
C
P
+
1μF
V
CP
CM4072
TDFN-10
C
S
EN_CP
EN_LDO
7
6
8
7
6
ENABLE CHARGE
PUMP
CONTROL
CIRCUIT
CS
C
BYP
+
ENABLE LDO
V
REF
LDO
8
V
OUT
PWM
0-200kHz
5
4
BYP
© 2005 California Micro Devices Corp. All rights reserved.
11/08/05
GND
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.cmd.com
1
PRELIMINARY
CM4072
PACKAGE / PINOUT DIAGRAM
(Pins Down View)
10 9 8 7 6
TOP VIEW
BOTTOM VIEW
(Pins Up View)
1 2 3 4 5
Pin 1
Marking
CM407
250xx
1 2 3 4 5
GND
PAD
10 9 8 7 6
Note: This drawing is not to scale.
CM4072-50DF/DE
10 Lead TDFN Package
PIN DESCRIPTIONS
LEAD(S)
1
2
NAME
DGND
V
IN
DESCRIPTION
Ground for the charge pump circuit. This should be connected to the system (noisy) ground.
Input power source for the device. Since the charge pump draws current in pulses at the
250kHz internal clock frequency, a low-ESR input decoupling capacitor is usually required close
to this pin to ensure low noise operation.
Charge pump output which is connected to the external reservoir capacitor C
S
. This should be a
low-ESR capacitor. When the voltage on this pin reaches about 5.8V then the charge pump
pauses until the voltage on this pin drops to about 5.7V. This gives rise to at least 100mV of 'rip-
ple' (the frequency and amplitude of this ripple depends upon values of C
P
and C
S
and also the
ESR of C
S
).
Ground reference for all internal circuits except the charge pump. This pin should be connected
to a "clean" low-noise analog ground
Bypass input connected to the internal voltage reference of the LDO regulator. An external
bypass capacitor C
BYP
of 0.1uF is recommended to minimize internal voltage reference noise
and maximize power supply ripple rejection.
EN_LDO (pin 6) and EN_CP (pin 7) are active-high TTL-level logic inputs to enable the linear
regulator and charge pump according to the following truth table:
EN_CP
(Pin 7)
1
1
0
0
EN_LDO
(Pin 6)
1
0
1
0
3
V
CP
4
5
GND
BYP
6, 7
EN_LDO,
EN_CP
CHARGE PUMP
Enabled
Enabled
Disabled
Disabled
REGULATOR
Enabled
Disabled
Disabled
Disabled
8
V
OUT
The regulated output. An output capacitor may be added to improve noise and load-transient
response. When the LDO regulator is disabled, an internal pull-down with a nominal resistance
of 50 ohms is activated to discharge the V
OUT
rail to GND
CP+ (pin 9) and CP- (pin 10) are used to connect the external "flying" capacitor C
P
to the charge
pump. The charge stored in C
P
is transferred to the reservoir capacitor C
S
at the 250kHz inter-
nal clock rate.
9, 10
CP+, CP-
© 2005 California Micro Devices Corp. All rights reserved.
2
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.cmd.com
11/08/05
PRELIMINARY
CM4072
Ordering Information
PART NUMBERING INFORMATION
Standard Finish
Leads
10
Package
TDFN-10
Ordering Part
Number
1
CM4072-50DF
Part Marking
CM407 250DF
Lead-free Finish
Ordering Part
Number
1
CM4072-50DE
Part Marking
CM407 250DE
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER
ESD Protection (HBM)
V
EN
Logic Input Voltage
V
IN,
V
OUT
Pin Voltages
Storage Temperature Range
Operating Temperature Range
Ambient
Junction
RATING
UNITS
V
V
V
°C
°C
°C
±
2000
(V
IN
+ 0.5) to (GND - 0.5)
+5.5 to (GND - 0.5)
-65 to +150
-40 to +85
-40 to +150
STANDARD OPERATING CONDITIONS
PARAMETER
Input Voltage Range (V
IN
)
Ambient Operating Temperature
VALUE
2.8 to 5.5
-40 to +85
200 (approx.)
0 to 200
0.1
0 to 100
UNITS
V
°C
°C/W
mA
μF
μF
θ
JA
of TDFN package on PCB
Output Load Current (I
OUT
)
C
BYP
C
OUT
RECOMMENDED EXTERNAL COMPONENTS
DEVICE
C
S
C
P
VALUE
2.2
1.0
UNITS
μF
μF
© 2005 California Micro Devices Corp. All rights reserved.
11/08/05
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.cmd.com
3
PRELIMINARY
CM4072
Specifications (cont’d)
ELECTRICAL OPERATING CHARACTERISTICS
(SEE NOTE 1)
SYMBOL
V
CP
V
OUT
V
R LOAD
V
R LINE
R
DISCHG
I
GND
PARAMETER
Charge Pump Output Voltage
Regulator Output Voltage
Load Regulation
Line Regulation
V
OUT
Discharge Resistance
LDO Regulator Ground Current via
the GND pin
CONDITIONS
V
OUT
= 5V, 1mA < I
OUT
< 100mA
V
IN
= 4.0V, 1mA < I
OUT
< 100mA
I
OUT
= 1mA to 100mA
Vary V
IN
from 3.0V to 5.0V
LDO regulator disabled, EN_LDO
grounded, V
IN
= 5V
Shutdown (EN_LDO grounded)
Regulator Enabled, I
OUT
= 0mA
Regulator Enabled, I
OUT
= 100mA
I
DGND
PSRR
Charge Pump Shutdown Current
via DGND pin
Power Supply Ripple Rejection
EN_CP grounded, V
IN
= 5V
I
OUT
= 100mA, C
BYP
=0.1μF, Note 2
f
= 100Hz
f
= 10kHz
BW=22Hz-22kHz, C
OUT
= 10μF,
C
BYP
= 0.1μF, I
OUT
= 100mA, Note 2
BW=22Hz-22kHz, C
P
= 1μF, C
S
=3μF,
C
OUT
= C
BYP
= 0.1μF, I
OUT
= 100mA,
Note 2
V
IH
V
IL
I
LIM
I
SC
T
JSD
T
HYS
EN_CP, EN_LDO Input High
Threshold
EN_CP, EN_LDO Input Low
Threshold
Overload Current Limit
Output Short Circuit Current
Thermal Shutdown Junction
Temperature
Thermal Shutdown Hysteresis
V
IN
= 5.0V
V
IN
= 5.0V
LDO Only, Note 2
LDO Only, Note 2
200
300
50
170
25
2.0
0.5
MIN
5.5
4.85
0.2
0.02
500
1
180
180
1
10
10
TYP
5.8
MAX
7
5.15
UNITS
V
V
%
%
Ω
μA
μA
μA
μA
42
42
35
38
dB
dB
μVrms
μVrms
e
NO
Output Voltage Noise
V
V
mA
mA
°C
°C
Note 1: Unless otherwise noted, electrical operating characteristics are specified with T
A
= 0 to 70°C, V
IN
= 5.0V, I
OUT
=100mA,
C
OUT
=10μF, C
P
= 1μF, C
S
= 10μF.
Note 2: These parameters are guaranteed by design and characterization.
© 2005 California Micro Devices Corp. All rights reserved.
4
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.cmd.com
11/08/05
PRELIMINARY
CM4072
Performance Information
p
1.00E-03
1.00E-04
Voltage [V]
1.00E-05
noise floor
Cs=1.5uF
1.00E-06
1.00E-07
1.00E-08
10
100
1000
Frequency [Hz]
10000
100000
Note: Noise peaks may appear for different values of C
P
, C
S
& I
OUT
, and are due to the ripple frequency of the charge pump (see later).
Figure 1. CM4072 Noise Spectrum ( T
A
= 25°C, C
P
=0.47μF, C
S
= 1.5μF,
C
OUT
= 10μF, C
BYP
= 0.1μF, I
OUT
=100mA )
70.0
60.0
50.0
PSRR [dB]
40.0
30.0
20.0
10.0
0.0
10
100
1000
Frequency [Hz]
10000
100000
Measured by forcing V
IN
voltage to 3.3V & 5.0V dc, then sweeping 100mV ac on V
IN
. C
OUT
= 10μF, C
BYP
= 0.1μF.
Figure 2. CM4072 PSRR (upper curve with V
IN
= 3.3V, lower curve
with V
IN
= 5V, I
OUT
= 100mA both cases)
© 2005 California Micro Devices Corp. All rights reserved.
11/08/05
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.cmd.com
5
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