DATASHEET
100V, 2A Peak, Half-Bridge Driver with Tri-Level PWM
Input and Adjustable Dead-Time
ISL78420
The ISL78420 is a 100V, 2A high frequency half-bridge NMOS
FET driver with a tri-level PWM input. With an operating supply
voltage range of 8V to 14V, it supports a 114V bootstrap bias for
driving the high-side NMOS in 100V half-bridge applications. This
part is a derivative of the industrial family of HIP2120-HIP2123
100V half-bridge drivers.
This driver is designed to work in conjunction with the
ISL78220
and
ISL78225
“Multi-Phase Interleaved Boost PWM Controller
with Light Load Efficiency Enhancement”. It can also be used in
applications where a standard half-bridge driver is needed.
This driver has a programmable dead-time to ensure
break-before-make operation between the high-side and low-side
MOSFET. A resistor is used to set the dead-time from 35ns to
220ns.
The PWM pin’s tri-level input allows control of the high-side and
low-side drivers with a single pin. When the PWM input is at logic
high, the high-side bridge FET is turned on and the low-side FET is
off. When the input is at logic low, the low-side bridge FET is
turned on and the high-side FET is turned off. When the input
voltage is in mid-level state, both the high and low-side bridge
FETs are turned off. The enable pin (EN), when low, also turns
both bridge FETs off. This EN input can be used when the
controller driving the ISL78420 does not utilize a tri-level output.
Both PWM and EN logic inputs are V
DD
tolerant.
The ISL78420 is offered in a 14 Ld HTSSOP package and
complies with 100V conductor spacing per IPC-2221. The device
is Automotive AEC-Q100 qualified for the temperature range of
-40°C to +125°C.
Features
• 114VDC bootstrap supply maximum voltage
• 2A source and sink driver for 100V half-bridge NMOS FETs
• Programmable dead-time prevents shoot-through; adjustable
from 35ns to 220ns with a single resistor
• Unique tri-level PWM input logic enables phase shedding when
using multiphase PWM controllers (e.g. ISL78220/225)
• On-chip 1Ω (dynamic) bootstrap diode
• 10ns rise and fall times with 1000pF load
• 8V to 14V operating voltage range
• Supply undervoltage lockout (UVLO)
• 14 Ld HTSSOP package compliant with 100V conductor
spacing guidelines per IPC-2221
• AEC-Q100 qualified
Applications
• Automotive applications
• Multiphase boost (ISL78220/225)
• Half-bridge DC/DC converter
• Class-D amplifiers
Related Literature
•
HIP2120, HIP2121,
“100V, 2A Peak, High Frequency Half-
Bridge Drivers with Adjustable Dead Time Control and PWM
Input”
•
ISL78220,
“6-Phase Interleaved Boost PWM Controller with
Light Load Efficiency Enhancement”
•
ISL78225,
“4-Phase Interleaved Boost PWM Controller with
Light Load Efficiency Enhancement”
•
UG006,
ISL78420EVAL1Z Evaluation Board User Guide
320
240
VIN
DEAD TIME DELAY (ns)
VOUT
ISL78225 PWM1
PWM2
4‐Phase
PWM3
Boost
Controller PWM4
PWM
VDD
EN
RDT
VSS
HB
ISL78420
EPAD
HO
HS
LO
200
160
140
120
100
80
60
40
T
A
= -40°C to +125°C
20
8
16
T = -40°C
T = +125°C
T = +85°C
T = +25°C
PHASE #1
PHASE #2
PHASE #3
PHASE #4
24
32
40
48 56 64 72 80
RESISTOR ON RDT PIN (kΩ)
FIGURE 1. NMOS DRIVER FOR 4-PHASE BOOST CONVERTER
FIGURE 2. DEAD-TIME vs TIMING RESISTOR
November 6, 2014
FN8296.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
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Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL78420
Block Diagram
VDD
BOOT
DIODE
UNDER
VOLTAGE
LEVEL
SHIFT
HO
HB
6.1V
HS
235k
-
+
DELAY
UNDER
VOLTAGE
DELAY
LO
PWM
165k
-
+
VSS
EN
210k
RDT
ISOLATED
ISL78420
EPAD
Pin Configurations
ISL78420ARTAZ
(10 LD 4x4 TDFN)
TOP VIEW
VDD
NC
HB
HO
1
2
3
10
9
LO
VSS
S
DE
NC
1
2
3
4
5
6
7
EPAD
(14 LD TSSOP)
TOP VIEW
14 VDD
13 LO
12
VSS
4
MM
ECO
R
NOT
HS
5
EW
R N
PWM
EPAD
FO
8
DED
EN
7
EN
6
RDT
S
IGN
NC
HB
HO
HS
NC
NC
11 PWM
10 EN
9
8
RDT
NC
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ISL78420
Pin Descriptions
10 LD
1
14 LD
14
SYMBOL
VDD
DESCRIPTION
Analog input supply voltage and positive supply for lower gate driver. Decouple this pin to ground with a 4.7µF
or larger high frequency ceramic capacitor to VSS. A 0.1µF ceramic decoupling capacitor placed close to VDD
and VSS pin is recommended.
High-side bootstrap supply voltage for upper gate driver referenced to HS. Connect the bootstrap capacitor to
this pin and HS.
High-side output driver connected to gate of high-side NMOS FET.
High-side gate driver reference node. Connect to source of high-side NMOS FET. Connect bootstrap capacitor
to this pin and HB.
Tri-level PWM input. Logic high drives HO high and LO low. Logic low drives HO low and LO high. In mid-level
state both outputs are driven low.
Output enable pin. When EN is low, HO = LO = 0. An internal 210kΩ pull-down resistor places EN in the low
state when the pin is left floating.
Analog supply ground. Decouple this pin to VDD with a 4.7µF or larger capacitor.
Low-side output driver connected to gate of low-side NMOS FET.
No Connect. This pin is isolated from all other pins. May optionally be connected to VSS.
A resistor connected between this pin and VSS adds dead time by adding delay time between the falling edge
of LO to rising edge of HO and falling edge of HO to rising edge of LO.
The EPAD is electrically isolated. It is recommended that the EPAD be connected to the VSS plane for heat
removal.
3
4
5
8
7
9
10
2
6
-
3
4
5
11
10
12
13
1, 2, 6,
7, 8
9
-
HB
HO
HS
PWM
EN
VSS
LO
NC
RDT
EPAD
Ordering Information
PART NUMBER
(Notes
1, 2, 3)
ISL78420AVEZ (Note
4)
Not Recommended for New Designs
ISL78420ARTAZ
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL78420.
For more information on MSL please see tech brief
TB363.
4. These packages meet compliance with 100V Conductor Spacing Guidelines per IPC-2221.
PART
MARKING
78420 AVEZ
78420 AZ
TEMP. RANGE
(°C)
-40 to +125
-40 to +125
PACKAGE
(Pb-Free)
14 Ld HTSSOP
10 Ld 4x4 TDFN
PKG.
DWG. #
M14.173B
L10.4x4
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ISL78420
Absolute Maximum Ratings
(Note
5)
Supply Voltage, V
DD
, V
HB
- V
HS
(Note
6)
. . . . . . . . . . . . . . . . . . -0.3V to 18V
PWM and EN Input Voltage . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
DD
+ 0.3V
Voltage on LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
DD
+ 0.3V
Voltage on HO . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
HS
- 0.3V to V
HB
+ 0.3V
Voltage on HS (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 110V
Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118V
Average Current in V
DD
to HB Diode . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
ESD Ratings
Human Body Model (Tested per AEC-Q100-002) . . . . . . . . . . . . . . . . . . 2kV
Charged Device Model (Tested per AEC-Q100-011). . . . . . . . . . . . . . 1.5kV
Latch-up (Tested per AEC-Q100-004) . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical) (Notes
7, 8)
JA
(°C/W)
JC
(°C/W)
14 Ld HTSSOP . . . . . . . . . . . . . . . . . . . . . . . . .
35
2.5
10 Ld TDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
4
Max Power Dissipation at +25°C in Free Air (Note
9)
14 Ld HTSSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5W
10 Ld TDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0W
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see
TB493
Maximum Recommended Operating
Conditions
(Note
5)
Supply Voltage, V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 14V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V
Voltage on HB (Note 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . V
HS
+ 8V to V
HS
+ 14V
HS Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. All voltages referenced to V
SS
unless otherwise specified.
6. The operating voltage from HB to GND is the sum of VDD and the HS voltage. The maximum operating voltage from HB to GND is recommended to
be under 114V.
7.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief
TB379.
8. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
9. Specified at published junction to ambient thermal resistance for a junction temperature of 150°C. Refer to
Note 7
for test condition to establish
junction to ambient thermal resistance.
V
DD
= V
HB
= EN = 12V, V
SS
= V
HS
= 0V. No Load on LO or HO, Unless Otherwise Specified. Boldface limits
apply across the operating temperature range, -40°C to +125°C.
T
A
= +25°C
PARAMETERS
SUPPLY CURRENTS
V
DD
Quiescent Current
I
DD8k
I
DD80k
V
DD
Operating Current
I
DDO8k
I
DDO80k
HB to HS Quiescent Current
HB to HS Operating Current
HB to V
SS
Leakage Current
HB to V
SS
Current, Operating
TRI-LEVEL PWM INPUT
High Level Threshold
V
PWMH
-
3.6
4.0
-
4.1
V
I
HB
I
HBO
I
HBS
I
HBSO
R
DT
= 8kΩ; PWM = 12V
R
DT
= 80kΩ; PWM = 12V
f
PWM
= 500kHz, R
DT
= 8kΩ
f
PWM
= 500kHz, R
DT
= 80kΩ
PWM = EN = 0V
f
PWM
= 500kHz
PWM = EN = 0V; V
HB
= V
HS
= 100V
f
PWM
= 500kHz; V
HB
= V
HS
= 100V
-
-
-
-
-
-
-
-
0.65
1.0
2.5
3.4
65
2.0
0.05
1.2
0.95
2.1
3
4
115
2.5
1.5
1.5
-
-
-
-
-
-
-
-
1
2.2
3
4
150
3
10
1.6
mA
mA
mA
mA
µA
mA
µA
mA
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
T
A
= -40°C to +125°C
MIN
(Note
10)
MAX
(Note
10)
UNITS
Electrical Specifications
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November 6, 2014
ISL78420
V
DD
= V
HB
= EN = 12V, V
SS
= V
HS
= 0V. No Load on LO or HO, Unless Otherwise Specified. Boldface limits
apply across the operating temperature range, -40°C to +125°C. (Continued)
T
A
= +25°C
PARAMETERS
Mid-Level Range
SYMBOL
V
MIDH
V
MIDL
Low Level Threshold
PWM Pull-up Resistor
PWM Pull-down Resistor
V
PWML
R
UP
R
DOWN
To internal 6.1V Reference
To V
SS
TEST CONDITIONS
Mid-Level Range Upper Limit
Mid-Level Range Lower Limit
MIN
3.0
-
0.8
-
-
TYP
3.4
1.6
1.1
235
165
MAX
-
2.1
-
-
-
T
A
= -40°C to +125°C
MIN
(Note
10)
2.9
-
0.7
-
-
MAX
(Note
10)
-
2.2
-
-
-
UNITS
V
V
V
kΩ
kΩ
Electrical Specifications
EN INPUT
Low Level Threshold
High Level Threshold
EN Pull-down Resistor
UNDERVOLTAGE PROTECTION
V
DD
Rising Threshold
V
DD
Threshold Hysteresis
V
HB
Rising Threshold
V
HB
Threshold Hysteresis
BOOTSTRAP DIODE
Low Current Forward Voltage
High Current Forward Voltage
Dynamic Resistance
LO GATE DRIVER
Low Level Output Voltage
High Level Output Voltage
V
OL_LO
V
OH_LO
I
LO
= 100mA Sink
I
LO
= 100mA Source
Voltage below VDD
V
OH_LO
= V
DD
- V
LO
V
LO
= 0V
V
LO
= 12V
-
-
0.25
0.25
0.4
0.4
-
-
0.5
0.5
V
V
V
DL
V
DH
R
D
I
VDD-HB
= 100µA
I
VDD-HB
= 100mA
R
D
=
V
D
/I
VDD-HB
I
VDD-HB
= 50mA and 100mA
-
-
-
0.6
0.7
0.8
0.7
0.9
1
-
-
-
0.8
1
1.5
V
V
Ω
V
DDR
V
DDH
V
HBR
V
HBH
6.8
-
6.2
-
7.3
0.6
6.9
0.6
7.8
-
7.5
-
6.5
-
5.9
-
8.0
-
7.8
-
V
V
V
V
V
ENL
V
ENH
R
EN
To V
SS
1.8
-
-
2.5
2.8
210
-
4.0
-
1.8
-
100
-
4.1
320
V
V
kΩ
Peak Pull-up Current
Peak Pull-down Current
HO GATE DRIVER
Low Level Output Voltage
High Level Output Voltage
I
OH_LO
I
OL_LO
-
-
2
2
-
-
-
-
-
-
A
A
V
OL_HO
V
OH_HO
I
HO
= 100mA Sink
I
HO
= 100mA Source
Voltage below V
HB
V
OH_HO
= V
HB
- V
HO
V
HO
= 0V
V
HO
= V
HB
-
-
0.25
0.25
0.4
0.4
-
-
0.5
0.5
V
V
Peak Pull-up Current
Peak Pull-down Current
I
OH_HO
I
OL_HO
-
-
2
2
-
-
-
-
-
-
A
A
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