CM3131
Triple Linear Voltage Regulator for DDR-I/-II Memory
Features
•
•
•
•
•
Integrated power solution for DDR-I and DDR-II
memory systems with few external components
Three all-linear regulators for V
DDQ
, V
TT
and
V
STBY
power supply applications
Lowest system cost and smallest footprint for
DDR power solutions
V
DDQ
regulator/driver utilizes external N-FET to
provide up to 15A current at 2.5V/1.8V
V
TT
source/sink regulator provides up to 2A at
1.25V for DDR-I systems or 0.65A at 0.9V for
the DDR-II memory controller (not DDR-II
memory)
LDO standby regulator provides up to 500mA at
2.5V for DDR-I and at 1.8V for DDR-II systems
Can be ganged for higher current applications
Over temperature and reverse current protection
Over current protection for V
STBY
and V
TT
regulator
Available in 8 lead and 14 lead PSOP packages
Lead-free versions available
Product Description
The CM3131 family of all-linear regulators provides
an integrated power solution for DDR-I/-II memory
systems in both run-time and standby modes of
operation. The CM3131 is ideal for designs
incorporating both a main 3.3V and a standby (3.3V
or 5V) supply. The CM3131 features three
independent linear regulators for V
DDQ
, V
TT
and V
STBY
supply regulation and will maintain an accuracy of
±1% across the operating temperature range.
The CM3131 is offered in two configurations. The
CM3131-01/11 drives a single external N-FET on a
single V
DDQ
rail. The CM3131-02 drives two external
unmatched N-FETs on two V
DDQ
rails. Each V
DDQ
rail
incorporates an adjustment pin (SENSE) to enable
setting V
DDQ
in the 2.2V to 2.8V range, supporting
DIMMs with different supply requirements or DDR-II
type devices.
The CM3131-01/11 is available in 8-lead PSOP
package and the CM3131-02 is available in 14-lead
PSOP package.
The CM3131 devices are also available with optional
lead-free finishing.
•
•
•
•
•
•
•
•
•
Applications
Desktop PCs, notebooks, and workstations
Set top boxes, digital TVs, printers
Embedded systems
Electrical Schematic
© 2004 California Micro Devices Corp. All rights reserved.
02/02/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
1
CM3131
PACKAGE / PINOUT DIAGRAM
TOP VIEW
TOP VIEW
NC
V
DDQ
DRIVE
V
TT
V
DDQ1
V
DDQ2
CM3131-02
SENSE2
DRIVE2
DRIVE1
V
STBY
GND
SEL
V
TT
CM3131-01/11
GND
V
STBY
NC
SENSE1
V
CC
EN
V
CC
SENSE
SEL/EN
PSOP-8
Note: These drawings are not to scale.
PSOP-14
PIN DESCRIPTIONS
PART NUMBER
-01
-11
-02
1
1
13
2
3
4
4
5
6
7
8
5
6
7
8
2
3
14
1
2
3
4
7
5
6
8
9
10
11
12
NAME
V
DDQ
/ V
DDQ1
V
TT
NC
GND
SEL
NC
EN
SENSE / SENSE1
V
CC
V
STBY
DRIVE / DRIVE1
DRIVE2
SENSE2
V
DDQ 2
DESCRIPTION
V
DDQ
input for V
REF
and V
DDQ
Output in Standby
V
TT
Output for termination resistors
No connection
Ground
Select Input, active low
No connection
Enable Input, active high
Sense Input, Adjusts V
DDQ
Rail
3.3V Main Input Supply
3.3V or 5V Standby Input Supply
Drive Output for V
DDQ
External n-FET
Drive Output for V
DDQ
External n-FET
Sense Input, Adjusts V
DDQ
Rail
V
DDQ
Input for V
REF
and V
DDQ
Output in Standby
Ordering Information
PART NUMBERING INFORMATION
STANDARD FINISH
PINS
8
8
14
PACKAGE
PSOP-8
PSOP-8
PSOP-14
ORDERING PART
NUMBER
1
CM3131-01SB
CM3131-11SB
CM3131-02SB
PART
MARKETING
CM3131-01SB
CM3131-11SB
CM3131-02SB
LEAD-FREE FINISH
ORDERING
PART NUMBER
1
CM3131-01SH
CM3131-11SH
CM3131-02SH
PART
MARKING
CM3131-01SH
CM3131-11SH
CM3131-02SH
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
© 2004 California Micro Devices Corp. All rights reserved.
02/02/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
2
CM3131
Functional Description
The CM3131-01 / -11 and CM3131-02 provide
power for DDR-I/DDR-II memories from three
voltage regulators on-chip with either one or two
external N-FETs respectively. There is an over-
temperature thermal shutdown if any of the
regulators overheat. Each regulator has reverse
current protection in the event of any being shut
down.
The linear regulator-driver/s with external N-FET/s
can provide up to 15A at 2.5V/1.8V for the V
DDQ
of
DDR-I/-II memory, from an input supply voltage of
2.8V-3.6V. An external feedback resistor divider,
connected to the SENSE1 pin, enables selection of
V
DDQ
output voltages from 2.2V to 2.8V for use with
DDR-I memories requiring other than 2.5V for V
DDQ
.
V
DDQ
= 1.25V x (R1+R2)/R2. When SENSE1 is
connected to GND or left open, V
DDQ
is fixed at
2.50V (and VTT at 1.25V). For DDR-II operation,
V
DDQ
can be set from 1.7V to 1.9V.
The V
TT
regulator is a linear source-sink regulator
powered from the V
DDQ
output that supplies the V
TT
supply required by DDR-I memory termination
resistors. This regulator sinks or sources up to 2A at
2.8V / 3.0V / 3.3V for DDR-I,
2.2V /2.5V / 3.3V for DDR-II
V
CC
PSOP-8
CM3131-01/11
1.25V to or from the DDR-I bus termination resistors.
For DDR-II applications, the regulator sinks or
sources 0.65A at 0.9V. The V
TT
output voltage
accurately tracks V
DDQ
/2 to 1%. When there is no
V
CC
provided, V
TT
is powered down and its output is
0V. This regulator has overload current limiting of
2.5A.
The standby regulator is a LDO regulator that is
powered from a standby voltage, V
STBY
, of 3.3V or
5V, and supplies a regulated output of up to 500mA
to the V
DDQ
of the DDR memory to enable it to retain
its contents during the standby mode. It provides
2.5V for DDR-I and 1.8V for DDR-II.
The CM3131-01 and CM3131-11 differ with regards
the selection of truth table for determining which S0-
S5 sequencing matrix the chip is set for. The
CM3131-02 has both EN and SEL pins to more
accurately define each Sx stage without monitoring
the V
CC
or V
STBY
voltages.
Two CM3131s can be ganged together to provide
V
DDQ
power to dual channels of DDR memory, and
the memory controller chip of any chip set.
V
DDQ
LDO Drive
DRIVE
Internal V
SBY
voltage
doubler ensures V
G
> 5.3V
Drives any N-FET with C
GS
<1200pF
FET
2.8V / 3.0V / 3.3V for DDR-I,
2.2V /2.5V / 3.3V for DDR-II
V
CC
CM3131-02
DRIVE1
V
DDQ
LDO Drives
DRIVE2
5V
STBY
/ 3.3V
STBY
V
DDQ1
V
DDQ
LDOs
V
DDQ
/ V
TT
Control
V
DDQ
C
SBY
C
CC
Linear
Source-Sink
V
TT
Reg
GND
V
DDQ2
N-FET1
N-FET2
5V
STBY
/ 3.3V
STBY
V
DDQ
LDO
V
DDQ
/ V
TT
Control
V
DDQ
V
DDQ
R1
V
DDQ
V
DDQ1
V
DDQ2
R1
C
DDQ2
R3
SEL / EN
SEL
SENSE
R2
GND
V
TT
C
TT
C
DDQ
C
SBY
C
CC
Linear
Source-Sink
V
TT
Reg
GND
V
TT
Only needed for
DDR-I if V
DDQ
is
not 2.5V, e.g. 2.6V
or 2.7V.
Set to 1.7V to
1.9V for DDR-II
SENSE1
SENSE2
R2
EN
R4
GND
C
DDQ1
V
TT
C
TT
V
TT
Examples of Single and Dual N-FET Drive Configurations
© 2004 California Micro Devices Corp. All rights reserved.
02/02/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
3
CM3131
Functional Description (cont’d)
V
CC
3V/3.3V
X
<V
CC MIN
X
V
STBY
SEL
5V/3.3V
ON
5V/3.3V
OFF
X
ON
<V
STBY MIN
OFF
V
DDQ 1,2
V
TT
V
DDQ
V
DDQ
/ 2
V
DDQ STBY
0V
0V
0V
0V
0V
Truth Table for CM3131-01
S to R
S0
S1
S2
S3
S4
S5
V
CC
3V/3.3V
3V/3.3V
3V/3.3V
3V/3.3V
<V
CC MIN
<V
CC MIN
V
STBY
5V/3.3V
5V/3.3V
5V/3.3V
5V/3.3V
5V/3.3V
5V/3.3V
SEL
ON
ON
ON
OFF
OFF
OFF
V
DDQ OUT
V
DDQ
V
DDQ
V
DDQ
V
DDQ STBY
0V
0V
V
TT OUT
V
DDQ
/ 2
V
DDQ
/ 2
V
DDQ
/ 2
0V
0V
0V
Sequencing Matrix for CM3131-01 for Suspend to RAM operation
No S to R
S0
S1
S2
S3
S4
S5
V
CC
3V/3.3V
3V/3.3V
3V/3.3V
<V
CC MIN
<V
CC MIN
<V
CC MIN
V
STBY
5V/3.3V
5V/3.3V
5V/3.3V
5V/3.3V
5V/3.3V
5V/3.3V
SEL
ON
ON
ON
ON
ON
ON
V
DDQ OUT
V
DDQ
V
DDQ
V
DDQ
0V
0V
0V
V
TT OUT
V
DDQ
/ 2
V
DDQ
/ 2
V
DDQ
/ 2
0V
0V
0V
Sequencing Matrix for CM3131-01 for Suspend to RAM Not Supported
V
CC
3V/3.3V
<V
CC MIN
<V
CC MIN
X
V
STBY
EN
5V/3.3V
ON
5V/3.3V
ON
X
OFF
<V
STBY MIN
OFF
V
DDQ OUT
V
TT OUT
V
DDQ
V
DDQ
/ 2
V
DDQ STBY
0V
0V
0V
0V
0V
Truth Table for CM3131-11
© 2004 California Micro Devices Corp. All rights reserved.
02/02/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
4
CM3131
Functional Description (cont’d)
S to R
S0
S1
S2
S3
S4
S5
V
CC
3V/3.3V
3V/3.3V
3V/3.3V
<V
CC MIN
<V
CC MIN
<V
CC MIN
V
STBY
5V/3.3V
5V/3.3V
5V/3.3V
5V/3.3V
5V/3.3V
5V/3.3V
EN
ON
ON
ON
ON
OFF
OFF
V
DDQ OUT
V
DDQ
V
DDQ
V
DDQ
V
DDQ STBY
0V
0V
V
TT OUT
V
DDQ
/ 2
V
DDQ
/ 2
V
DDQ
/ 2
0V
0V
0V
Sequencing Matrix for CM3131-11 for Suspend to RAM operation
V
CC
3V/3.3V
<V
CC MIN
X
0V
<V
CC MIN
V
STBY
5V/3.3V
5V/3.3V
<V
STBY MIN
X
X
SEL
ON
OFF
OFF
ON
X
EN
ON
ON
ON
ON
OFF
V
DDQ OUT
V
TT OUT
V
DDQ
V
DDQ STBY
0V
0V
0V
V
DDQ
/ 2
0V
0V
0V
0V
Truth Table for CM3131-02
Table 3
S0
S1
S2
S3
S4
S5
V
CC
3V/3.3V
3V/3.3V
3V/3.3V
<V
CC MIN
<V
CC MIN
<V
CC MIN
V
STBY
5V/3.3V
5V/3.3V
5V/3.3V
5V/3.3V
X
X
SEL
ON
ON
ON
OFF
ON
ON
EN
ON
ON
ON
ON
OFF
OFF
V
DDQ OUT
V
TT OUT
V
DDQ
V
DDQ
V
DDQ
V
DDQ STBY
0V
0V
V
DDQ
/ 2
V
DDQ
/ 2
V
DDQ
/ 2
0V
0V
0V
Sequencing Matrix for CM3131-02 for Suspend to RAM operation
© 2004 California Micro Devices Corp. All rights reserved.
02/02/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
5
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
