AS4C2M32S
2M x 32 bit Synchronous DRAM (SDRAM)
Confidential
Features
Fast access time: 5.5/5.5 ns
Fast Clock rate:
200/166/143
MHz
Fully synchronous operation
Internal pipelined architecture
Four internal banks (512K x 32bit x 4bank)
Programmable Mode
- CAS Latency: 2 or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: Sequential or Interleaved
- Burst-Read-Single-Write
Burst stop function
Individual byte controlled by DQM0-3
Auto Refresh and Self Refresh
Operating temperature range
- Commercial (0 ~ 70°C)
- Industrial (-40 ~ 85°C)
4096 refresh cycles/64ms
Single +3.3V ± 0.3V power supply
Interface: LVTTL
86-pin 400 x 875 mil plastic TSOP II
package, 0.50mm pin pitch
- Pb and Halogen Free
(Rev.
3.0, May.
/2014)
Overview
The 64Mb SDRAM is a high-speed CMOS
synchronous DRAM containing 64 Mbits. It is
internally configured as a quad 512K x 32 DRAM with
a synchronous interface (all signals are registered on
the positive edge of the clock signal, CLK). Each of
the 512K x 32 bit banks is organized as 2048 rows by
256 columns by 32 bits. Read and write accesses to
the SDRAM are burst oriented; accesses start at a
selected location and continue for a programmed
number of locations in a programmed sequence.
Accesses begin with the registration of a
BankActivate command which is then followed by a
Read or Write command.
The SDRAM provides for programmable Read or
Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence. The refresh functions, either Auto or Self
Refresh are easy to use.
By having a programmable mode register, the
system can choose the most suitable modes to
maximize
its performance. These devices are well suited
for applications requiring high memory bandwidth.
Table 1. Key Specifications
AS4C2M32S
tCK3
Clock Cycle time(min.)
tAC3
tRAS
tRC
Access time from CLK (max.)
Row Active time(min.)
Row Cycle time(min.)
-5/6/7
5/6/
ns
5.5/5.5 ns
42/49 ns
60/70 ns
Table 2.Ordering Information
Part Number
AS4C2M32S-6TIN
AS4C2M32S-6TCN
AS4C2M32S-7TCN
AS4C2M32S-5TCN
Frequency
166MHz
166MHz
143MHz
200MHz
Package
86-pin TSOP II
86-pin TSOP II
86-pin TSOP II
86-pin TSOPII
Temperature
Industrial
Commercial
Commercial
Commercial
Temp Range
-40 ~ 85°C
0 ~ 70°C
0 ~ 70°C
0 ~ 70°C
T: indicates TSOP II package
N: indicates Pb and Halogen Free
Confidential
1
Rev.
3.0
May.
/2014
AS4C2M32S
Figure 1. Pin Assignment (Top View)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10/AP
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
Confidential
2
Rev. 3.0
May. /2014
AS4C2M32S
Figure 2. Block Diagram
CLK
CKE
CS#
RAS#
CAS#
WE#
2048 x 256 x 32
CELL ARRAY
(BANK #0)
Column Decoder
Row
Decoder
CLOCK
BUFFER
DQ0
DQ Buffer
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
DQ31
DQM0~3
A10/AP
COLUMN
COUNTER
MODE
REGISTER
2048 x 256 x 32
CELL ARRAY
(BANK #1)
Column Decoder
A0
A9
BA0
BA1
~
ADDRESS
BUFFER
2048 x256 x 32
CELL ARRAY
(BANK #2)
Column Decoder
Row
Decoder
REFRESH
COUNTER
Row
Decoder
2048 x 256 x 32
CELL ARRAY
(BANK #3)
Column Decoder
Confidential
3
Rev. 3.0
Row
Decoder
May. /2014
~
AS4C2M32S
Pin Descriptions
Symbol Type Description
CLK
Input
Clock:
CLK is driven by the system clock. All SDRAM input signals are sampled on the
positive edge of CLK. CLK also increments the internal burst counter and controls the
output registers.
Input
Clock Enable:
CKE activates (HIGH) and deactivates (LOW) the CLK signal. If CKE goes
low synchronously with clock (set-up and hold time same as other inputs), the internal clock
is suspended from the next clock cycle and the state of output and burst address is frozen
as long as the CKE remains low. When all banks are in the idle state, deactivating the clock
controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except
after the device enters Power Down and Self Refresh modes, where CKE becomes
asynchronous until exiting the same mode. The input buffers, including CLK, are disabled
during Power Down and Self Refresh modes, providing low standby power.
Input
Bank Activate:
BA0 and BA1 define to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied. The bank address BA0 and BA1 is used latched
in mode register set.
Table 3. Pin Details
CKE
BA0,
BA1
A0-A10 Input
Address Inputs:
A0-A10 are sampled during the BankActivate command (row address A0-
A10) and Read/Write command (column address A0-A7 with A10 defining Auto Precharge)
to select one location out of the 512K available in the respective bank. During a Precharge
command, A10 is sampled to determine if all banks are to be precharged (A10 = HIGH).
The address inputs also provide the op-code during a Mode Register Set or Special Mode
Register Set command.
CS#
Input
Chip Select:
CS# enables (sampled LOW) and disables (sampled HIGH) the command
decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external
bank selection on systems with multiple banks. It is considered part of the command code.
Input
Row Address Strobe:
The RAS# signal defines the operation commands in conjunction
with the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS#
and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate
command or the Precharge command is selected by the WE# signal. When the WE# is
asserted "HIGH," the BankActivate command is selected and the bank designated by BA is
turned on to the active state. When the WE# is asserted "LOW," the Precharge command is
selected and the bank designated by BA is switched to the idle state after the precharge
operation.
Input
Column Address Strobe:
The CAS# signal
conjunction with the RAS# and WE# signals and
When RAS# is held "HIGH" and CS# is asserted
asserting CAS# "LOW." Then, the Read or Write
"LOW" or "HIGH."
defines the operation commands in
is latched at the positive edges of CLK.
"LOW," the column access is started by
command is selected by asserting WE#
RAS#
CAS#
WE#
Input
Write Enable:
The WE# signal defines the operation commands in conjunction with the
RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is used
to select the BankActivate or Precharge command and Read or Write command.
DQM0 - Input
Data Input/Output Mask: Data Input Mask:
DQM0-DQM3 are byte specific. Input data is
DQM3
masked when DQM is sampled HIGH during a write cycle. DQM3 masks DQ31-DQ24,
DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0 masks DQ7-DQ0.
DQ0- Input/
Data I/O:
The DQ0-31 input and output data are synchronized with the positive edges of
DQ31 Output CLK. The I/Os are byte-maskable during Reads and Writes.
NC
V
DDQ
V
SSQ
V
DD
V
SS
-
No Connect:
These pins should be left unconnected.
Supply
DQ Power:
Provide isolated power to DQs for improved noise immunity.
Supply
DQ Ground:
Provide isolated ground to DQs for improved noise immunity.
Supply
Power Supply:
+3.3V0.3V
Supply
Ground
Confidential
4
Rev. 3.0
May. /2014
AS4C2M32S
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 4
shows the truth table for the operation commands.
Table 4. Truth Table (Note (1), (2))
Command
BankActivate
BankPrecharge
PrechargeAll
Write
Write and AutoPrecharge
Read
Read and Autoprecharge
Mode Register Set
No-Operation
Burst Stop
Device Deselect
AutoRefresh
SelfRefresh Entry
SelfRefresh Exit
Clock Suspend Mode Entry
Power Down Mode Entry
Clock Suspend Mode Exit
Power Down Mode Exit
Data Write/Output Enable
State
Idle
(3)
Any
Any
Active
(3)
Active
(3)
Active
(3)
Active
(3)
Idle
Any
Active
(4)
Any
Idle
Idle
Idle
(SelfRefresh)
CKE
n-1
CKE
n
DQM
(6)
BA
0,1
A
10
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
H
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
H
H
X
X
X
X
V
V
V
V
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
V
V
X
V
V
V
V
L
H
L
A
0-9
X
X
CS# RAS# CAS# WE#
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
H
H
X
L
L
X
H
X
V
X
H
X
X
H
X
H
H
H
L
L
L
L
L
H
H
X
L
L
X
H
X
V
X
H
X
X
H
X
H
L
L
L
L
H
H
L
H
L
X
H
H
X
H
X
V
X
H
X
X
H
X
X
Row address
Column
H address
(A0 ~ A7)
Column
address
H
(A0 ~ A7)
OP code
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
H
L
L
H
L
H
L
H
L
X
H
L
X
Active
Any
(5)
Active
Any
(PowerDown)
Active
Data Mask/Output Disable
Active
H
X
H
X
X
X
X
X
X
Note:
1. V = Valid, X = Don't care, L = Logic low, H = Logic high
2. CKE
n
signal is input level when commands are provided.
CKE
n-1
signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BA signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
6. DQM0-3
Confidential
5
Rev. 3.0
May. /2014
FPGA/CPLD
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