DATASHEET
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716,
ISL88813
Designed with high reset threshold accuracy and low power
consumption, the ISL88705, ISL88706, ISL88707,
ISL88708, ISL88716 and ISL88813 devices are
microprocessor supervisors that are designed to monitor
power-supply and battery functions in microprocessor
systems. They can help to lower system cost, reduce board
space requirements and increase the reliability of systems.
These devices provide essential functions such as supply
voltage supervision by asserting a reset output during
power-up and power-down as well as during brownout
conditions. An auxiliary voltage monitor is provided for
detecting power failures warning the system of low battery
conditions or presence detection. In addition, an
independent watchdog timer helps to monitor
microprocessor activity every 1.6s (typical). An active-low
manual reset is offered and reset signals remain asserted
until V
DD
returns to proper operating levels.
Users can increase the nominal 200ms power-on reset
time-out delay by adding an external capacitor to the C
POR
pin on the ISL88707 and ISL88708.
FN8092
Rev 6.00
November 30, 2015
Features
• Fixed-Voltage Options Allow Precise Monitoring of +3.0V,
+3.3V, and +5.0V Power Supplies
• Additional Voltage Monitor for Power-Fail Detection or
Low-Battery Warning
- Monitors Voltages Down to 1.25V
- Adjustable Power-Fail Input Threshold
• Watchdog Timer Capability With 1.6s Time-out
• Both RST and RST Outputs Available
• 140ms Minimum Reset Pulse Width with Option to
Customize Using an External Capacitor
• Manual Reset Input on all Devices
• Reset Signal Valid Down to V
DD
= 1V
• Accurate ±1.8% Voltage Threshold
• Immune to Power-Supply Transients
• Ultra Low 10µA Maximum Supply Current at 3V
• Pb-Free (RoHS Compliant)
Applications
• Portable/Battery Powered Equipment
• Notebook/Desktop Computer Systems
• Designs Using DSPs, Microcontrollers or Microprocessors
• Controllers
• Intelligent Instruments
• Communications Systems
• Industrial Equipment
Pinouts
ISL88705, ISL88706
(8 LD SOIC)
(PDIP - NO LONGER AVAILABLE)
TOP VIEW
MR
V
DD
GND
PFI
1
2
3
4
8
7
6
5
WDO
RST
WDI
PFO
ISL88716, ISL88813
(8 LD SOIC)
(PDIP - NO LONGER AVAILABLE)
TOP VIEW
MR
V
DD
GND
PFI
1
2
3
4
8
7
6
5
WDO
RST
WDI
PFO
ISL88707, ISL88708
(8 LD SOIC)
(PDIP - NO LONGER AVAILABLE)
TOP VIEW
MR
V
DD
GND
PFI
1
2
3
4
8
7
6
5
RST
RST
C
POR
PFO
FN8092 Rev 6.00
November 30, 2015
Page 1 of 16
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
Ordering Information
PART NUMBER
(Note)
ISL88705IP846Z
(No longer available, recommended
replacement: ISL88705IB846Z)
ISL88813IP846Z
(No longer available, recommended
replacement: ISL88813IB846Z)
ISL88707IP846Z
(No longer available, recommended
replacement: ISL88707IB846Z)
ISL88706IP844Z
(No longer available, recommended
replacement: ISL88706IB844Z)
ISL88708IP844Z
(No longer available, recommended
replacement: ISL88708IB844Z)
ISL88706IP831Z
(No longer available, recommended
replacement: ISL88706IB831Z)
ISL88708IP831Z
(No longer available, recommended
replacement: ISL88708IB831Z)
ISL88706IP829Z
(No longer available, recommended
replacement: ISL88706IB829Z)
ISL88708IP829Z
(No longer available, recommended
replacement: ISL88708IB829Z)
ISL88706IP826Z
(No longer available, recommended
replacement: ISL88706IB826Z)
ISL88716IP826Z
(No longer available, recommended
replacement: ISL88716IB826Z)
ISL88708IP826Z
(No longer available, recommended
replacement: ISL88708IB826Z)
ISL88705IB846Z*
ISL88813IB846Z*
ISL88707IB846Z*
ISL88706IB844Z*
ISL88708IB844Z*
ISL88706IB831Z*
ISL88708IB831Z*
ISL88706IB829Z*
ISL88708IB829Z*
ISL88706IB826Z*
ISL88716IB826Z*
ISL88708IB826Z*
ISL88705EVAL1
PART
MARKING
V
TH
TEMP RANGE
(°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
(RoHS Compliant)
8 Ld PDIP**
8 Ld PDIP**
8 Ld PDIP**
8 Ld PDIP**
8 Ld PDIP**
8 Ld PDIP**
8 Ld PDIP**
8 Ld PDIP**
8 Ld PDIP**
8 Ld PDIP**
8 Ld PDIP**
8 Ld PDIP**
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
PKG. DWG. #
MDP0031
MDP0031
MDP0031
MDP0031
MDP0031
MDP0031
MDP0031
MDP0031
MDP0031
MDP0031
MDP0031
MDP0031
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
88705 I46Z 4.64V
88813 I46Z 4.64V
88707 I46Z 4.64V
88706 I44Z 4.38V
88708 I44Z 4.38V
88706 I31Z 3.09V
88708 I31Z 3.09V
88706 I29Z 2.92V
88708 I29Z 2.92V
88706 I26Z 2.63V
88716 I26Z 2.63V
88708 I26Z 2.63V
88705 I46Z 4.64V
88813 I46Z 4.64V
88707 I46Z 4.64V
88706 I44Z 4.38V
88708 I44Z 4.38V
88706 I31Z 3.09V
88708 I31Z 3.09V
88706 I29Z 2.92V
88708 I29Z 2.92V
88706 I26Z 2.63V
88716 I26Z 2.63V
88708 I26Z 2.63V
Evaluation Board
*Add “-TK” suffix for Tape and Reel Packaging. Please refer to TB347 for details on reel specifications.
**Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
FN8092 Rev 6.00
November 30, 2015
Page 2 of 16
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
Functional Block Diagrams
V
DD
RST
± V
REF
MR
PB
WDO
WDI
WDT
WDI
WDT
POR
± V
REF
MR
PB
WDO
POR
RST
± V
REF
MR
PB
OSC
POR
RST
V
DD
V
DD
RST
C
POR
PFI
± V
REF
PF
GND
PFO
PFI
± V
REF
PF
GND
PFO
PFI
± V
REF
PF
GND
PFO
ISL88705, ISL88706
ISL88716, ISL88813
ISL88707, ISL88708
FN8092 Rev 6.00
November 30, 2015
Page 3 of 16
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
Pin Descriptions
ISL88705, ISL88716, ISL88707,
ISL88706 ISL88813 ISL88708 NAME
1
1
1
MR
DESCRIPTION
Manual Reset Input.
A reset signal is generated when this input is pulled low. The MR input is an
active low debounced input to which a user can connect a push-button to add manual reset capability
or drive with a signal. The MR pin has an internal 20kpull-up.
Power Supply Terminal.
The voltage at this pin is compared against an internal factory-programmed
voltage trip point, V
TH1
. A reset is first asserted when the device is initially powered up to ensure that
the power supply has stabilized. Thereafter, reset is again asserted whenever V
DD
falls below V
TH1
.
The device is designed with hysteresis to help prevent chattering due to noise and is immune to brief
power-supply transients. The voltage threshold V
TH1
is specified in the part number suffix.
Ground Connection
Power-Fail Input
This is an auxiliary monitored voltage input with a 1.25V threshold that causes PFO
state to follow the PFI input state.
Power-Fail Output.
This output goes high if the voltage on PFI is greater than 1.25V, otherwise PFO
stays low.
2
2
2
V
DD
3
4
5
3
4
5
3
4
5
6
GND
PFI
PFO
C
POR
Adjustable POR Time-out Delay Input.
Connecting an external capacitor from C
POR
to ground
allows the user to increase the Power-On Reset time-out (t
POR
) from the nominal 200ms.
WDI
Watchdog Input.
The Watchdog Input takes an input from a microprocessor and ensures that it
periodically toggles the WDI pin, otherwise the internal nominal 1.6s watchdog timer runs out, then
reset is asserted and WDO is pulled low. The internal Watchdog Timer is cleared whenever the WDI
sees a rising or falling edge or the device is manually reset. Floating WDI or connecting WDI to a
high-impedance three-state buffer disables the watchdog feature.
Active-Low Reset Output.
The RST output is an active low output with an internal PMOS pull-up
that is pulled low to GND when reset is asserted. Reset is asserted whenever:
1. The device is first powered up
2. V
DD
falls below its minimum voltage sense level or
3. MR is asserted.
The reset output continues to be asserted for typically 200ms after V
DD
rises above the reset
threshold or MR input goes from low to high. A watchdog time-out will not trigger a reset unless WDO
is connected to MR.
6
6
7
7
RST
7
8
RST
Active-High Reset Output.
The RST pin functions identically to its complementary RST output but
is an active high push-pull output. RST is set high to V
DD
when reset is asserted. See the RST in “Pin
Descriptions” on page 4 for more details on conditions that cause a reset.
Watchdog Output.
This output is pulled low when the nominal 1.6s internal Watchdog Timer expires
and periodically resets until the watchdog is cleared. WDO also goes low during low V
DD
conditions.
Whenever V
DD
is below the reset threshold, WDO stays low. However, unlike RESET, WDO does
not have a minimum pulse width. As soon as V
DD
rises above the reset threshold, WDO goes high
with no delay.
8
8
WDO
FN8092 Rev 6.00
November 30, 2015
Page 4 of 16
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
Absolute Maximum Ratings
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on any Pin with Respect to GND . . . . . . . . . . . -1.0V to +7V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Thermal Information
Thermal Resistance (Typical, Note 1)
JA
(°C/W)
PDIP Package* (4-layer test board) . . . . . . . . . . . . .
83
SOIC Package (4-layer test board) . . . . . . . . . . . . .
110
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
Recommended Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
CONDITIONS
MIN
2.0
V
DD
= 5V, WDT Inactive
V
DD
= 3V, WDT Inactive
10
8
TYP
MAX
5.5
19
10
100
100
UNITS
V
µA
µA
nA
nA
SYMBOL
V
DD
I
DD
PARAMETER
Supply Voltage Range
I
LI
I
LO
Input Leakage Current (PFI)
Output Leakage Current
VOLTAGE THRESHOLDS
V
TH1
Fixed V
DD
Voltage Trip Point
4.556
4.301
3.034
2.867
2.583
V
TH1HYST
Hysteresis at V
TH1
Input
Temperature = +25°C
V
TH1
= 4.64V
V
TH1
= 4.38V
V
TH1
= 3.09V
V
TH1
= 2.92V
V
TH1
= 2.63V
RST AND RST
V
OL
Reset Output Voltage Low
V
DD
3.3V, Sinking 2.5mA
V
DD
< 3.3V, Sinking 1.5mA
V
OH
RST Output Voltage High
V
DD
3.3V, Sourcing 2.5mA
V
DD
< 3.3V, Sourcing 1.5mA
RST Output Voltage High
V
DD
3.3V, Sourcing 0.8mA
V
DD
< 3.3V, Sourcing 0.5mA
t
RPD
t
POR
C
LOAD
V
TH
to Reset Asserted Delay
POR Time-Out Delay
Load Capacitance on Reset Pins
C
POR
is open
140
V
DD
- 0.6
V
DD
- 0.6
V
DD
- 0.6
V
DD
- 0.6
0.05
0.05
V
DD
- 0.4
V
DD
- 0.4
V
DD
- 0.4
V
DD
- 0.4
45
200
5
260
0.40
0.40
V
V
V
V
V
V
µs
ms
pF
4.640
4.380
3.090
2.920
2.630
46
44
37
29
31
4.724
4.459
3.146
2.973
2.677
V
V
V
V
V
mV
mV
mV
mV
mV
FN8092 Rev 6.00
November 30, 2015
Page 5 of 16
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