Supertex inc.
Three-Channel, Closed-Loop,
Switch Mode LED Driver IC
Features
General Description
►
Switch mode controller for single-switch
converters
►
Gate drivers optimized for driving Logic Level FETs
♦
0.25A sourcing
♦
0.5A sinking
►
Typical ±2% absolute and string-to-string current
accuracy (with ±1% sense resistors)
►
High PWM dimming ratio up to 5000:1
►
10-40V input range
►
Constant frequency operation up to 1.0MHz
►
On-chip clock or external clock option
►
Programmable slope compensation
►
Linear and PWM dimming
►
Output short circuit protection
►
Output over voltage protection
►
Hiccup mode protection
HV9985
The HV9985 is a three-channel peak current mode PWM
controller for driving single switch converters in a constant
output current mode. It can be used for driving either RGB LEDs
or multiple channels of white LEDs.
The HV9985 features a 40V linear regulator, which provides a
5.0V supply to power the IC. The switching frequencies of the
three converters in the IC are controlled either with an external
clock signal (the channels operate at a switching frequency
of 1/12th of the external clock frequency) or using the internal
oscillator. The three channels are positioned 120° out-of-phase
to reduce the input current ripple. Each converter is driven by a
peak current mode controller with output current feedback.
The three output currents can be individually dimmed using
either linear or PWM dimming. The IC also includes three
disconnect FET drivers which enable high PWM dimming ratios
and also helps to disconnect the input in case of an output short
circuit condition. The HV9985 includes hiccup mode protection
for both open LED and short circuit condition to prevent the IC
from shutting down in the case of intermittent faults.
Applications
►
RGB backlight applications
►
Boost, buck & SEPIC topologies
►
Multiple string white LED driver applications
Typical Application Circuit
L1
D1b (Optional)
Q1a
C
IN
C
IN1
D1a
R
OVP1a
C
O1
C
SC1
C
VDD
C
VDD1
R
SC1
CS1
R
CS1
R
OVP1b
VDD
VIN
GND
EN
RT
VDD1
GT1
GND1 OVP1
FLT1
FDBK1
COMP1
Q1b
(One Channel Shown)
PWMD1
CLK
SKIP
REF1
HV9985
R
T
C
C1
C
REF1
R
REF1
REF
R
S
C
SKIP
Doc.# DSFP-HV9985
C051513
Supertex inc.
www.supertex.com
HV9985
GATE1
FDBK2
GATE2
GND1
CS2
Part Number
HV9985K6-G*
HV9985K6-G M935*
HV9985QP-G*
Package Option
40-Lead QFN (6x6)
40-Lead QFN (6x6)
44-Lead QSOP
Packing
490/Tray
2000/Reel
1000/Reel
VDD1
FLT1
CS1
COMP1
1
40
GND3
GATE3
GND2
VDD2
Ordering Information
Pin Configuration
FLT2
VDD3
FLT3
CS3
COMP3
-G denotes a lead (Pb)-free / RoHS compliant package
* Product is not recommended for new designs. Contact factory for availiability.
Absolute Maximum Ratings
Parameter
VIN to GND
VDD to GND, VDD 1-3 to GND
All other pins to GND
Junction temperature
Storage ambient temperature range
Continuous power dissipation
(T
A
= +25°C)
Value
-0.3V to +45V
-0.3V to +6.0V
-0.3V to (V
DD
+ 0.3V)
-40°C to +125°C
-65°C to +150°C
4000mW
FDBK1
REF1
OVP1
VIN
VDD
EN
GND
FDBK3
REF3
OVP3
CLK
RT
NC
PWMD1
PWMD2
PWMD3
COMP2
GND
SKIP
OVP2
REF2
Stresses beyond those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond
those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
40-Lead QFN
(top view)
REF1
OVP1
VIN
VDD
EN
NC
GND
NC
COMP2
REF2
OVP2
SKIP
NC
PWMD1
PWMD2
PWMD3
NC
NC
RT
CLK
OVP3
REF3
1
44
FDBK1
COMP1
CS1
FLT1
VDD1
NC
GATE1
GND1
FDBK2
CS2
FLT2
GATE2
GND2
VDD2
GND3
GATE3
NC
VDD3
FLT3
CS3
COMP3
FDBK3
Thermal Resistance
Package
40-Lead QFN
44-Lead QSOP
θ
ja
24
O
C/W
50
O
C/W
θ
ja
for QFN package is based on a 4 layer PCB as per JESD51-9
θ
ja
for QSOP package is based on a 4 layer PCB as per JESD51-7
44-Lead QSOP
(top view)
Product Marking
HV9985
LLLLLL
YYWW
AAACCC
L = Lot Number
YY = Year Sealed
WW = Week Sealed
A = Assembler ID
C = Country of Origin
= “Green” Packaging
Top Marking
H V 9985QP
YYW W AA A
L L L L LL L L L L
Bottom Marking
CCCCCCCCCCC
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin
A = Assembler ID
= “Green” Packaging
Package may or may not include the following marks: Si or
Package may or may not include the following marks: Si or
40-Lead QFN
Doc.# DSFP-HV9985
C051513
44-Lead QSOP
Supertex inc.
www.supertex.com
2
NC
NC
HV9985
0
O
C<T
A
<+85
O
C, otherwise the specifications are at T
A
= 25
O
C. V
IN
= 24V, V
DD1
= V
DD2
= V
DD3
= V
DD
unless otherwise noted.)
Electrical Characteristics
(The * denotes the specifications which apply over the full operating ambient temperature range
Sym
Input
V
INDC
I
INSD
I
IN
Input DC supply voltage
Shut-down mode supply current
Supply current
*
*
-
10
-
-
-
-
-
40
200
1.5
V
μA
mA
DC input voltage
EN ≤ 0.8V
EN ≥ 2.0V; PWMD1 = PWMD2 =
PWMD3 = GND
V
IN
= 10 - 40V; EN = HIGH;
PWMD1-3 = V
DD
;
GATE1-3 = 2.0nF; CLK = 6.0MHz
V
DD
rising
V
DD
falling
---
---
V
EN
= 5.0V
---
---
V
PWMD
= 5.0V
Parameter
Min
Typ
Max
Units
Conditions
Internal Regulator
V
DD
UVLO
RISE
UVLO
HYST
V
EN(LO)
V
EN(HI)
R
EN
V
PWMD(lo)
V
PWMD(hi)
R
PWMD
Internally regulated voltage
V
DD
under voltage lockout threshold
V
DD
under voltage hysteresis
EN input low voltage
EN input high voltage
EN pull down resistor
PWMD input low voltage
PWMD input high voltage
PWMD pull down resistor
*
-
-
*
*
-
*
*
-
4.75
4.25
-
-
2.0
50
-
2.0
50
5.00
-
250
-
-
100
-
-
100
5.25
4.75
-
0.8
-
150
0.8
-
150
V
V
mV
V
V
kΩ
V
V
kΩ
Enable Input
PWM Dimming (PWMD1, PWMD2 and PWMD3)
Gate (GATE1, GATE2 and GATE3)
I
SOURCE
I
SINK
T
RISE
T
FALL
D
MAX
V
OVP,rising
V
OVP,HYST
GATE short circuit current, sourcing
GATE sinking current
GATE output rise time
GATE output fall time
Maximum duty cycle
Over voltage rising trip point
Over voltage hysteresis
#
#
*
*
#
*
-
0.25
0.5
-
-
-
1.13
-
-
-
-
-
91.7
1.25
125
-
-
85
45
-
1.37
-
A
A
ns
ns
%
V
mV
V
GATE
= 0V
V
GATE
= V
DD
C
GATE
= 2.0nF
C
GATE
= 2.0nF
---
OVP rising
OVP falling
Over Voltage Protection (OVP1, OVP2 and OVP3)
Current Sense (CS1, CS2 and CS3)
T
BLANK
T
DELAY
R
DIS
#
*
Leading edge blanking
Delay to output of GATE
Discharge resistance for slope
compensation
*
-
*
100
-
-
-
-
-
250
200
100
ns
ns
Ω
---
100mV overdrive to the current
sense comparator
GATE = Low
Denotes specifications guaranteed by design.
The specifications which apply over the full operating temperature range at 0
O
C < T
A
< +85
O
C are guaranteed by design and characterization.
Doc.# DSFP-HV9985
C051513
3
Supertex inc.
www.supertex.com
HV9985
0
O
C<T
A
<+85
O
C, otherwise the specifications are at T
A
= 25
O
C. V
IN
= 24V, V
DD1
= V
DD2
= V
DD3
= V
DD
unless otherwise noted.)
Electrical Characteristics
(The * denotes the specifications which apply over the full operating ambient temperature range
Sym
GB
A
V
V
CM
V
O
G
M
V
OFFSET
I
BIAS
R
RATIO
f
OSC1
K
SW
P
HI
1
T
OFF,MIN
T
ON,MIN
V
CLOCK,HI
V
CLOCK,LO
Oscillator
F
osc1
F
osc2
F
osc
T
RISE,FAULT
T
FALL,FAULT
T
BLANK,SC
G
SC
V
omin
T
OFF
SKIP timer
I
HC,SOURCE
V
SKIP
#
*
Parameter
Gain bandwidth product
Open loop DC gain
Input common-mode range
Output voltage range
Transconductance
Input offset voltage
Input bias current
Resistor divider ratio (∆V
CS
/∆V
COMP
)
Oscillator frequency
Oscillator divider ratio
GATE1-GATE2 phase delay
GATE1-GATE3 phase delay
Minimum CLOCK low time
Minimum CLOCK high time
CLOCK input high
CLOCK input low
#
-
#
#
-
-
#
#
-
#
#
#
#
#
*
*
-
-
#
*
*
*
-
-
*
Min
-
65
-0.3
-
500
-5.0
-
-
-
-
-
-
50
50
2.0
-
110
440
-
-
-
400
1.85
0.15
-
Typ
1.0
-
-
-
625
-
0.5
0.11
500
12.0
120
240
-
-
-
-
125
500
-
-
-
-
2.0
-
-
Max
-
-
3.0
V
DD
750
5.0
1.0
-
-
-
-
-
-
-
-
0.8
140
560
1000
300
200
700
2.15
0.25
250
Units
MHz
dB
V
-
μA/V
mV
nA
-
kHz
-
O
O
Conditions
75pF capacitance at COMP pin
Output open
---
---
---
---
---
---
F
CLOCK
= 6.0MHz
---
---
---
---
---
---
---
RT = 400kΩ
RT = 100kΩ
---
500pF capacitor at FLT pin
500pF capacitor at FLT pin
---
---
REF = GND
FDBK = 2 • REF + 0.1V
Internal Transconductance Opamp (Gm1, Gm2 and Gm3)
External Clock Input
ns
ns
V
V
kHz
kHz
kHz
ns
ns
ns
-
V
ns
Switching frequency (common for
all channels)
Switching frequency range
Fault output rise time
Fault output fall time
Blanking time
Gain for short circuit comparator
Minimum current limit threshold
Propagation time for short circuit
detection
Current source at SKIP pin used for
hiccup mode protection
ΔVoltage swing at SKIP pin
Disconnect Driver (FLT1, FLT2 and FLT3)
Short Circuit Protection (all three channels)
-
#
-
-
5.0
1.5
-
-
μA
V
---
---
Denotes specifications guaranteed by design.
The specifications which apply over the full operating temperature range at 0
O
C < T
A
< +85
O
C are guaranteed by design and characterization.
Doc.# DSFP-HV9985
C051513
4
Supertex inc.
www.supertex.com
HV9985
Internal Block Diagram
VIN
EN
VDD
POR
FDA
FDB
FDC
0.1V
+
-
S
Q
R
2V
Fault
Linear
Regulator
UVLO
GND
POR
5µA
SKIP
+
-
DIS
FC
Fault
Common Circuitry
Circuitry for a single channel
PWMDA
CLKA
CLK A
CLK B
CLK C
θ=0
θ = 120
θ = 240
CLK
RT
VDD1
S
R
Q
Q
+
-
FC
GATE1
PWMD1
100k
PWMDA
BLANKING
CLKA
1
CS1
GND1
REF1
FDBK1
1
FLT1
PWMDA
FC
R
1
-
+
0.2V
8R
2
PWMDA
+
-
BLANKING
PWMDA
OVP1
+
REF
-
FDA
DIS
1
COMP1
Doc.# DSFP-HV9985
C051513
5
Supertex inc.
www.supertex.com
NXP MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
