NB3W800L
3.3 V 100/133 MHz
Differential 1:8 HCSL-
Compatible Push-Pull Clock
ZDB/Fanout Buffer for PCIe
)
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Description
The NB3W800L is a low−power 8−output differential buffer that
meets all the performance requirements of the DB800ZL
specification. The NB3W800L is capable of distributing the reference
clocks for Intel
®
QuickPath Interconnect (Intel QPI and UPI), PCIe
Gen1/Gen2/Gen3/Gen4, SAS, SATA, and Intel Scalable Memory
Interconnect (Intel SMI) applications. A fixed, internal feedback path
maintains low drift for critical QPI applications.
Features
MARKING
DIAGRAM
1
1 48
CASE 485DP
NB3W800L
AWLYYWWG
•
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•
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8 Differential Clock Output Pairs @ 0.7 V
Low−power NMOS Push−pull HCSL Compatible Outputs
Cycle−to−cycle Jitter <50 ps
Output−to−output Skew <50 ps
Input−to−output Delay Variation <100 ps
PCIe Phase Jitter: Gen3 <1.0 ps, Gen4 <0.5 ps RMS
QPI 9.6GT/s 12UI Phase Jitter <0.2 ps RMS
Pseudo−External Fixed Feedback for Lowest Input−to−Output Delay
Individual OE Control; Hardware Control of Each Output
PLL Configurable for PLL Mode or Bypass Mode (Fanout
Operation)
100 MHz or 133 MHz PLL Mode Operation; Supports PCIe, QPI
and UPI Applications
Selectable PLL Bandwidth; Minimizes Jitter Peaking in Downstream
PLL’s
SMBus Programmable Configurations
Spread Spectrum Compatible; Tracks Input Clock Spreading for Low
EMI
These are Pb−Free Devices
NB3W800L
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
NB3W800LMNG
NB3W800LMNTXG
NB3W800LMNTWG
Package
QFN48
(Pb−Free)
QFN48
(Pb−Free)
QFN48
(Pb−Free)
Shipping
†
490 / Tray
2500 / Tape &
Reel
2500 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2017
1
February, 2017 − Rev. 3
Publication Order Number:
NB3W800L/D
NB3W800L
8
OE[7:0]#
FB_OUT
FB_OUT#
SSC Compatible
PLL
DIF[7:0]
DIF[7:0]#
MUX
CLK_IN
CLK_IN#
100M_133M#
HBW_BYP_LBW#
Control
Logic
PWRGD/PWRDN#
SDA
SCL
Figure 1. Simplified Block Diagram
Table 1. OE AND POWER PIN TABLE
Inputs
PWRGD/
PWRDN#
0
1
CLK_IN/
CLK_IN#
X
Running
OE# Hardware Pins & Control Register Bits
SMBUS
Enable Bit
X
0
1
1
OE# Pin
X
X
0
1
DIF/DIF# [7:0]
Hi−Z
Hi−Z
Running
Hi−Z
Outputs
FB_OUT/
FB_OUT#
Hi−Z
Running
Running
Running
PLL State
OFF
ON
ON
ON
Table 2. FUNCTIONALITY AT POWER−UP (PLL MODE)
100M_133M#
1
0
CLK_IN MHz
100.00
133.33
DIF(7:0)
CLK_IN
CLK_IN
Table 5. PLL OPERATING MODE READBACK TABLE
HBW_BYP_LBW#
Low (Low BW)
Mid (Bypass)
High (High BW)
Byte0, bit 7
0
0
1
Byte 0, bit 6
0
1
1
Table 3. POWER CONNECTIONS
Pin Number
VDD
44
3
10, 15, 19, 27, 34, 38, 42
GND
49
2
49
Description
Analog PLL
Analog Input
DIF clocks
Table 6. TRI−LEVEL INPUT THRESHOLDS
Level
Low
Mid
High
Voltage
<0.8 V
1.2<Vin<1.8 V
Vin > 2.2 V
Table 7. PLL OPERATING MODE
Table 4. SMBus ADDRESS
Address
D8
+ Read/Write bit
R
HBW_BYP_LBW#
Low
Mid
High
NOTE:
PLL is OFF in Bypass Mode
Mode
PLL Lo BW
Bypass
PLL Hi BW
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2
NB3W800L
HBW_BYP_LBW#
100M_133M#
VDDA
DIF7#
OE7#
48
1
PWRGD/PWRDN#
GNDA
VDDR
CLK_IN
CLK_IN#
SDA
SCL
FB_OUT_NC#
FB_OUT_NC
VDD
OE0#
NC
12
13
DIF0#
DIF1#
DIF2#
VDD
OE1#
VDD
OE2#
OE3#
DIF0
DIF1
DIF2
NC
Bottom EPAD
must be connected
to Ground
OE6#
37
36
DIF6#
DIF6
VDD
DIF5#
DIF5
OE5#
OE4#
DIF4#
DIF4
VDD
DIF3#
DIF3
25
24
DIF7
VDD
Figure 2. Pin Configuration
Table 8. PIN DESCRIPTIONS
Pin #
1
2
3
4
5
6
7
8
Pin Name
PWRGD/PWRDN#
GNDA
VDDR
CLK_IN
CLK_IN#
SDA
SCL
FB_OUT_NC#
Type
IN
GND
PWR
IN
IN
I/O
IN
OUT
Description
3.3 V Input notifies device to sample latched inputs and start up on first high assertion,
or exit Power Down Mode on subsequent assertions. Low enters Power Down Mode.
Ground for Input Receiver and PLL Core
3.3 V power for differential input clock (receiver).
This VDD should be treated as an analog power rail and filtered appropriately.
0.7 V Differential true input
0.7 V Differential complementary Input
Data pin of SMBus circuitry
Clock pin of SMBus circuitry
Complementary half of differential feedback output provides feedback signal to the PLL for
synchronization with input clock to eliminate phase error. This pin should NOT be connected on
the circuit board; the feedback is internal to the package.
True half of differential feedback output provides feedback signal to the PLL for synchronization
with the input clock to eliminate phase error. This pin should NOT be connected on the circuit
board; the feedback is internal to the package.
Power supply, nominal 3.3 V
Active low input for enabling DIF pair 0. This pin has an internal pull−down.
1 = disable outputs, 0 = enable outputs
No Connection.
0.7 V differential true clock output
0.7 V differential complementary clock output
Power supply, nominal 3.3 V
0.7 V differential true clock output
9
FB_OUT_NC
OUT
10
11
12
13
14
15
16
VDD
OE0#
NC
DIF0
DIF0#
VDD
DIF1
PWR
IN
N/A
OUT
OUT
PWR
OUT
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3
VDD
NC
NC
NC
NB3W800L
Table 8. PIN DESCRIPTIONS
Pin #
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Pin Name
DIF1#
OE1#
VDD
NC
DIF2
DIF2#
OE2#
OE3#
DIF3
DIF3#
VDD
DIF4
DIF4#
OE4#
OE5#
DIF5
DIF5#
VDD
DIF6
DIF6#
OE6#
VDD
DIF7
DIF7#
OE7#
VDD
NC
VDDA
NC
NC
100M_133M#
HBW_BYP_LBW#
GND
Type
OUT
IN
PWR
N/A
OUT
OUT
IN
IN
OUT
OUT
PWR
OUT
OUT
IN
IN
OUT
OUT
PWR
OUT
OUT
IN
PWR
OUT
OUT
IN
PWR
N/A
PWR
N/A
N/A
IN
IN
PWR
Description
0.7 V differential complementary clock output
Active low input for enabling DIF pair 1. This pin has an internal pull−down.
1 =disable outputs, 0 = enable outputs
Power supply, nominal 3.3 V
No Connection.
0.7 V differential true clock output
0.7 V differential complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull−down.
1 = disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 3. This pin has an internal pull−down.
1 = disable outputs, 0 = enable outputs
0.7 V differential true clock output
0.7 V differential complementary clock output
Power supply, nominal 3.3 V
0.7 V differential true clock output
0.7 V differential complementary clock output
Active low input for enabling DIF pair 4. This pin has an internal pull−down.
1 = disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 5. This pin has an internal pull−down.
1 =disable outputs, 0 = enable outputs
0.7 V differential true clock output
0.7 V differential complementary clock output
Power supply, nominal 3.3 V
0.7 V differential true clock output
0.7 V differential complementary clock output
Active low input for enabling DIF pair 6. This pin has an internal pull−down.
1 = disable outputs, 0 = enable outputs
Power supply, nominal 3.3 V
0.7 V differential true clock output
0.7 V differential complementary clock output
Active low input for enabling DIF pair 7. This pin has an internal pull−down.
1 = disable outputs, 0 = enable outputs
Power supply, nominal 3.3 V
No Connection.
3.3 V power for the PLL core.
No Connection.
No Connection.
3.3 V Input to select operating frequency. See Functionality Table for Definition
Trilevel input to select High BW, Bypass or Low BW mode.
See PLL Operating Mode Table for Details.
EPAD, must be connected to Ground
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NB3W800L
Table 9. ABSOLUTE MAXIMUM RATINGS
Symbol
VDD, VDDA
V
IL
V
IH
V
IHSMB
Ts
Tj
ESD prot
q
JA
q
JC
Parameter
3.3 V Supply Voltage (Notes 1, 2)
Input Low Voltage (Note 1)
Input High Voltage (Note 1)
Input High Voltage (Note 1)
Storage Temperature (Note 1)
Junction Temperature (Note 1)
Input ESD protection (Note 1)
Thermal Resistance, Junction−to−Ambient
Thermal Resistance, Junction−to−Case
Human Body Model
Still air
2000
17
7
Except for SMBus interface
SMBus clock and data pins
−65
Conditions
VDD for core logic and PLL
GND−0.5
V
DD
+ 0.5
5.5
150
125
Min
Typ
Max
4.6
Units
V
V
V
V
°C
°C
V
°C/W
°C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Guaranteed by design and characterization, not tested in production.
2. Operation under these conditions is neither implied nor guaranteed.
Table 10. ELECTRICAL CHARACTERISTICS–CLOCK INPUT PARAMETERS (HCSL−COMPATIBLE)
(V
DD
= V
DDA
= 3.3 V
±5%,
T
A
= 0°C
*
70°C), See Test Loads for Loading Conditions. (Note 5)
Symbol
V
IHCLK_IN
V
ILCLK_IN
V
COM
V
SWING
dv/dt
I
IN
d
tin
J
DIFIn
Parameter
Input High Voltage
-
CLK_IN (Note 3)
Input Low Voltage
-
CLK_IN (Note 3)
Input Common Mode
Voltage
-
CLK_IN (Note 3)
Input Amplitude
-
CLK_IN (Note 3)
Input Slew Rate
-
CLK_IN (Notes 3, 4)
Input Leakage Current (Note 3)
Input Duty Cycle (Note 3)
Input Jitter
-
Cycle to Cycle (Note 3)
Conditions
Differential inputs
(single−ended measurement)
Differential inputs
(single−ended measurement)
Common Mode Input Voltage
(Single−ended measurement)
Peak to Peak (differential)
Measured differentially
V
IN
= V
DD
,
V
IN
= GND
Measurement from differential
waveform
Differential Measurement
Min
600
V
SS
-
300
300
300
0.35
−5
45
Typ
800
0
Max
1150
300
1000
1450
8
5
55
125
Units
mV
mV
mV
mV
V/ns
mA
%
ps
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Guaranteed by design and characterization, not tested in production.
4. Slew rate measured through
±75
mV window centered around differential zero.
5. Test configuration is; Rs = 27
W,
2 pF for 85
W
transmission line.
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