The Si9150 synchronous buck regulator controller is ideally
suited for high-efficiency step down converters in battery-pow-
ered equipment. Combined with the Si9943DY MOSFET half-
bridge, a 90 % efficient, 7.5 W, 3.3 V or 5 V power supply can
be implemented using standard surfacemount assembly tech-
niques. The wide input range allows operation from NiCd or
NiMH battery packs using six to ten cells.
Over-current protection is achieved by sensing the on-state
voltage drop across the high side P-Channel MOSFET, which
eliminates the need for a current sense resistor.
Duty ratios of 0 to 100 % and switching frequencies up to
300 kHz are possible. The IC can be disabled by pulling EN low
(I
DD
= 100 µA), or the 2.5 V reference can be maintained, with
all other functions disabled, by pulling STBY low (I
DD
= 500 µA).
The Si9150 is available in both standard and lead (Pb)-free
14-pin SOIC and rated for the commercial temperature
range of 0 to 70 °C (C suffix), and the industrial temperature
range of - 40 to + 85 °C (D suffix).
FEATURES
•
•
•
•
•
•
•
•
6 to 16.5 V Input Range (Si9150CY)
Voltage-Mode PWM Control
Low-Current Standby Mode
Enable Control
Dual 100 mA Output Drivers
2 % Band Gap Reference
Multiple Converters Easily Synchronized
Over-Current Protection
FUNCTIONAL BLOCK DIAGRAM
V
DD
14
20 µA
500 kΩ
1
0.5 V
Power Down
UVLO
13
P-GATE
EN
R
Q
S
2
STBY
4.7 V
Oscillator,
Comparators,
& Error Amp
Reference
Generator
Current
Limit
+
-
Strobe
7
I
SENSE
-
3
SS
Ref
Gen
Error
Amplifier
+
-
5
FB
4
COMP
9
C
T
R
T
10
8
SYNC
11
GND
1V
+
R
Q
OSC
S
Break-
Before-
Make
Logic
V
DD
12
N-GATE
5W
6
V
REF
Synchronous Buck Regulator Controller
Document Number: 70020
S-40752-Rev. F, 19-Apr-04
www.vishay.com
1
Si9150
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltages Referenced to GND
V
DD
I
SENSE
Input
All Other Inputs
P-Gate, N-Gate Continuous Source/Sink Current
Storage Temperature
Operating Junction Temperature (T
J
)
Power Dissipation (Package)
a
Thermal Impedance (Θ
JA
)
Product is End of Life 3/2014
Limit
18
- 2 V to V
DD
+ 2 V
- 0.3 V to V
DD
+ 0.3 V
50
- 65 to 125
150
14-Pin SOIC (Y Suffix)
b
14-Pin SOIC
900
140
Unit
V
mA
°C
mW
°C/W
Notes:
a. Device Mounted with all leads soldered or welded to PC board.
b. Derate 7.2 mW/°C.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS
a
Parameter
Reference
T
A
= 25 °C
Output Voltage
Oscillator
Maximum Frequency
f
MAX
f
OSC
V
OSC
f
TEMP
I
B
A
VOL
V
OS
BW
I
OUT
PSRR
V
CL
t
d
V
UVLO
V
HYS
I
SS
T
A
= 25 °C, V
DD
= 10 V
T
A
= 25 °C
Upper Threshold
5.4
0.10
Source, V
COMP
= 2.50 V
Sink, V
COMP
= 1.0 V
1
50
0.43
1
C
OSC
= 94.3 pF, R
OSC
= 28.7 kΩ
T
A
= 25 °C
f
C
OSC
= 212 pF, R
OSC
= 41.2 kΩ
T
A
= 25 °C
f
T
A
= 25 °C, 100 kHz
V
DD
= 10 V, T
MIN
to T
MAX
V
FB
= V
REF
60
255
85
2.05
-5
300
100
2.65
±3
25
72
10
1.5
- 0.30 - 0.20
2.5
70
0.49
500
5.7
0.17
20
0.55
1000
6.0
0.25
5.38
0.10
0.9
48
0.43
25
1
345
115
2.85
+5
500
58
255
85
2.05
-6
300
100
2.65
±4
25
72
10
1.5
- 0.30 - 0.15
2.5
70
0.49
500
5.7
0.17
20
0.55
1000
6.01
0.26
30
345
kHz
115
2.85
+6
750
V
%
nA
dB
mV
MHz
mA
dB
V
ns
V
µA
V
REF
Measured at Feedback
e
Pin 5
T
MIN
to T
MAXd
2.45
2.425
2.50
2.500
2.55
2.575
2.45
2.40
2.50
2.500
2.55
V
2.60
Symbol
Test Conditions
Unless Otherwise Specified
6.0
≤
V
DD
≤
16.5 V
Limits
C Suffix 0 to 70 °C
Min
b
Typ
c
Max
b
Limits
D Suffix - 40 to 85 °C
Min
b
Typ
c
Max
b
Unit
Initial Accuracy
Oscillator Ramp Amplitude
Temperature Stability
d
Error Amplifier
Input BIAS Current
Open Loop Voltage Gain
d
Offset Voltage
Unity Gain Bandwidth
d
Output Current
Power Supply Rejection
Protection
Current Limit Threshold Voltage
Current Limit Delay to Output
d
Undervoltage Lockout Voltage
Undervoltage Hysteresis
Softstart Pull-Up Current
www.vishay.com
2
Document Number: 70020
S-40752-Rev. F, 19-Apr-04
Product is End of Life 3/2014
Si9150
Vishay Siliconix
SPECIFICATIONS
a
Parameter
Supply
Supply Current (Enable Low)
Supply Current (Enable High)
Supply Current (STBY Low)
Output
Output High Voltage
Output Low Voltage
Output Resistance
Rise Time
d
Fall Time
Logic
Delay to Output
Enable Pull-Up Resistance
STBY Pull-Up Current
Turn-On Threshold
Turn-Off Threshold
t
d(EN)
R
EN
I
STBY
V
ENH
V
ENL
T
A
= 25 °C, V
STBY
= 0 V
V
DD
= 10 V
V
DD
= 10 V, Rising Input Voltage
V
DD
= 10 V, Falling Input Voltage
- 25
6
2
Transition High to Low
0.25
500
- 20
6.8
3.75
- 15
8
5
- 28
6
2
1
0.25
500
- 20
6.8
3.75
- 12
8
5
1
µs
kΩ
µA
V
d
Symbol
Test Conditions
Unless Otherwise Specified
6.0
≤
V
DD
≤
16.5 V
Limits
C Suffix 0 to 70 °C
Min
b
Typ
60
c
Limits
D Suffix - 40 to 85 °C
b
Unit
Max
Min
b
Typ
60
c
Max
b
I
OFF
I
CC
I
SB
V
OH
V
OL
R
OUT
t
r
t
f
I
OUT
= 10 mA, V
DD
= 10 V
I
OUT
= - 10 mA, V
DD
= 10 V
I
OUT
= 100 mA, V
DD
= 10 V
C
L
= 800 pF, V
DD
= 10 V
9.75
C
L
= 0 pF, f
OSC
= 100 kHz
V
DD
= 10 V
100
3.0
500
9.7
0.25
100
3.0
550
µA
mA
µA
2.2
300
2.2
300
0.3
10
30
30
25
70
70
V
Ω
ns
10
30
30
20
60
60
Notes:
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. Guaranteed by design, not subject to production test.
e. The voltage reference is trimmed with the feedback (Pin 5) connected to compensation (Pin 4) so that the effect of the error amplifier’s input
offset voltage is eliminated.
f. C
OSC
includes the PC board’s parasitic capacitance.
TYPICAL CHARACTERISTICS
25 °C unless noted
Document Number: 70020
S-40752-Rev. F, 19-Apr-04
www.vishay.com
3
Si9150
Vishay Siliconix
1000
Product is End of Life 3/2014
Frequency (kHz)
100
50 pF
100 pF
150 pF
200 pF
10
10
100
r
OSC
- Oscillator Resistance (kΩ)
1000
Oscillator Characteristics
www.vishay.com
4
Document Number: 70020
S-40752-Rev. F, 19-Apr-04
Product is End of Life 3/2014
Si9150
Vishay Siliconix
PIN CONFIGURATION AND ORDERING INFORMATION
SOIC
EN
STANDBY
SS
COMP
FB
V
REF
I
SENSE
1
2
3
4
5
6
7
Top View
14
13
12
11
10
9
8
V
DD
P-GATE
N-GATE
GND
R
T
C
T
SYNC
ORDERING INFORMATION
Part Number
Si9150CY
Si9150CY-T1
Si9150CY-T1-E3
Si9150DY
Si9150DY-T1
Si9150DY-T1-E3
- 40 to 85 °C
0 to 70 °C
SOIC-14
Temperature Range
Package
PIN DESCRIPTION
Pin 1: EN
When this pin is low, the IC is shut down. After a low signal
is applied to EN, then COMP, REF, R
T
, and C
T
settle toward
ground; N-GATE, STBY and Soft-Start are grounded; and P-
GATE is pulled high. The current consumption is no more
than 100 µA in this state. This input’s threshold has substan-
tial hysteresis so that a capacitor to GND can be used to
delay restart after the current limit is activated. After V
ENH
is
exceeded, one clock cycle elapses before N-GATE and P-
GATE are enabled. EN is pulled up to V
DD
through a 500 k
resistor and is pulled down internally when the current limit is
triggered.
Pin 2: STBY
Has a function similar to EN. The differences are that the EN
pin is unaffected, that the reference is still available, that bias
currents are still present internally, and that this pin’s pull up
current is present. This pin should be used to disable an
application if the reference voltage is still needed.
Pin 3: Soft-Start (SS)
This pin limits the maximum voltage that the error amplifier
can output. A capacitor between this pin and ground will limit
the rate at which the duty factor can increase during initial
power up, during a restart when EN or STBY goes high, or
after the current limit is triggered. A capacitor here can pre-
vent an application from triggering the Si9150’s current limit
during startup. Soft-Start is pulled low if either EN or STBY is
low.
Pin 4: Compensation (COMP)
This pin is tied directly to the output of the error amplifier. The
feedback network which insures the stability of an application
uses this pin. COMP settles low when either EN or STBY is
pulled low.
Pin 5: Feedback (FB)
This pin is attached directly to the inverting input of the error
amplifier. This pin is used to regulate the power supply’s out-
put voltage.
Pin 6: Reference (V
REF
)
The internal 2.5 V reference generator is attached to this pin
through a 5
Ω
resistor. A 0.1 µF bypass capacitor is needed
to suppress noise. Also note that the generator has an open
emitter; it will not pull down. The maximum current that the
generator will source before it current limits is about 10 mA.
Many parts of the IC use this voltage, so it is important not to
overload the reference generator.
Pin 7: I
SENSE
This pin should be attached to the switched node (the
drains of the application’s P-Channel and N-Channel MOS-
FETs). If the voltage between V
DD
and this pin is more then
0.46 V while the P-GATE is low, the current limit is acti-
vated. The current limit is relatively slow to prevent false
triggering due to noise. Activating the current limit causes
EN to be pulled to GND. I
SENSE
may be operated from V
DD
+ 2 V to GND - 2 V. For operation above 13.5 V
DD
a filter
(1 kΩ, 33 pF) is needed between the MOSFET drains and
the I
SENSE
pin; refer to Figure 1.
Pin 8: SYNC
This pin forces the clock to reset when low, and is also pulled
low when the clock resets itself. Thus if several Si9150’s
have their sync pins shorted together, they will be synchro-
nized; the shortest duration clock will control the other
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