36 Mb (1M x 36 & 2M x 18)
DDR-II (Burst of 2) CIO Synchronous SRAMs
.
I
May 2009
Features
• 1M x 36 or 2M x 18.
• On-chip delay-locked loop (DLL) for wide data
valid window.
• Common data input/output bus.
• Synchronous pipeline read with self-timed late
write operation.
• Double data rate (DDR-II) interface for read and
write input ports.
• Fixed 2-bit burst for read and write operations.
• Clock stop support.
• Two input clocks (K and K) for address and con-
trol registering at rising edges only.
• Two input clocks (C and C) for data output con-
trol.
• Two echo clocks (CQ and CQ) that are delivered
simultaneously with data.
• +1.8V core power supply and 1.5, 1.8V V
DDQ
,
used with 0.75, 0.9V V
REF
.
• HSTL input and output levels.
• Registered addresses, write and read controls,
byte writes, data in, and data outputs.
• Full data coherency.
• Boundary scan using limited set of JTAG 1149.1
functions.
• Byte write capability.
• Fine ball grid array (FBGA) package
- 15mm x 17mm body size
- 1mm pitch
- 165-ball (11 x 15) array
• Programmable impedance output drivers via 5x
user-supplied precision resistor.
Description
The 36Mb
IS61DDB21M36
and
IS61DDB22M18
are synchronous, high-performance
CMOS static
random access memory
(SRAM) devices.
These
SRAMs have a common I/O
bus. The rising
edge
of K clock initiates the
read/write
operation, and
all internal operations are
self-
timed.
Refer to the
Timing Reference Diagram for Truth
Table
on page
8
for a description of the basic opera-
tions of these
DDR-II (Burst of 2) CIO
SRAMs.
The input addresses are registered on all rising
edges of the K clock. The DQ bus operates at
double data rate for reads and writes. The following
are registered internally on the rising edge of the K
clock:
•
•
•
•
•
Read and write addresses
Address load
Read/write enable
Byte writes
Data-in
The following are registered on the rising edge of
the K clock:
• Byte writes
• Data-in for second burst addresses
Byte writes can change with the corresponding data-
in to enable or disable writes on a per-byte basis. An
internal write buffer enables the data-ins to be regis-
tered one cycle later than the write address. The first
data-in burst is clocked with the rising edge of the
next K clock, and the second burst is timed to the
following rising edge of the K clock.
During the burst read operation, at the first burst the
data-outs are updated from output registers off the
second rising edge of the C clock (1.5 cycles later).
At the second burst, the data-outs are updated with
the third rising edge of the corresponding C clock
(see page
8).
The K and K clocks are used to time
the data-outs whenever the C and C clocks are tied
high.
The device is operated with a single +1.8V power
supply and is compatible with HSTL I/O interfaces.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.
F
05/08/09
1
36 Mb (1M x 36 & 2M x 18)
DDR-II (Burst of 2) CIO Synchronous SRAMs
I
7
BW
1
BW
0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
V
SS
/SA*
NC
DQ17
NC
DQ15
NC
NC
V
REF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
®
x36 FBGA Pinout
(Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/SA*
DQ27
NC
DQ29
NC
DQ30
DQ31
V
REF
NC
NC
DQ33
NC
DQ35
NC
TCK
3
SA
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
V
DDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW
2
BW
3
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
SA
0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
• The following pins are reserved for higher densities: 2A for 144Mb, 10A for 72Mb.
• BW
0
controls writes to DQ0–DQ8; BW
1
controls writes to DQ9–DQ17; BW
2
controls writes to DQ18–DQ26; BW
3
controls
writes to DQ27–DQ35.
x18 FBGA Pinout
(Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/SA*
DQ9
NC
NC
NC
DQ12
NC
V
REF
NC
NC
DQ15
NC
NC
NC
TCK
3
SA
NC
NC
DQ10
DQ11
NC
DQ13
V
DDQ
NC
DQ14
NC
NC
DQ16
DQ17
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW
1
NC/SA
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
SA
0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
NC/SA
BW
0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
DQ7
NC
NC
NC
NC
V
REF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
• The following pin is reserved for higher densities: 2A for 72Mb, 7A for 144Mb, 5B for 288Mb.
• BW
0
controls writes to DQ0–DQ8; BW
1
controls writes to DQ9–DQ17
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.
F
05/08/09
36 Mb (1M x 36 & 2M x 18)
DDR-II (Burst of 2) CIO Synchronous SRAMs
I
Description
Input clock.
Input clock for output data control.
Output echo clock.
DLL disable when low.
Burst count address input.
1M x 36 address inputs.
2M x 18 address inputs.
®
Pin Description
Symbol
K, K
C, C
CQ, CQ
Doff
SA
0
SA
SA
DQ0–DQ8
DQ9–DQ17
DQ18–DQ26
DQ27–DQ35
DQ0–DQ8
DQ9–DQ17
R/W
LD
6B, 6A
6P, 6R
11A, 1A
1H
6C
9A, 4B, 8B, 5C, 7C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R, 4R, 5R, 7R,
8R, 9R
3A, 9A, 4B, 8B, 5C, 7C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R, 4R, 5R,
7R, 8R, 9R
11P, 11M, 11L, 11K, 11J, 11F, 11E, 11C, 11B
10P, 11N, 10M, 10K, 10J, 11G, 10E, 11D, 10C
3B, 3D, 3E, 3F, 3G, 3K, 3L, 3N, 3P
2B, 3C, 2D, 2F, 2G, 3J, 2L, 3M, 2N
11P, 10M, 11L, 11K, 10J, 11F, 11E, 10C, 11B
2B, 3D, 3E, 2F, 3G, 3K, 2L, 3N, 3P
4A
8A
Pin Number
1M x 36 DQ pins
2M x 18 DQ pins
Read/write control. Read when active high.
Synchronizes load. Loads new address
when low.
1M x 36 byte write control, active low.
2M x 18 byte write control, active low.
Input reference level.
Power supply.
Output power supply.
BW
0,
BW
1,
BW
2,
BW
3
7B, 7A, 5A,5B
BW
0,
BW
1
V
REF
V
DD
V
DDQ
V
SS
ZQ
TMS, TDI, TCK
TDO
7B, 5A
2H, 10H
5F, 7F, 5G, 7G, 5H, 7H, 5J, 7J, 5K, 7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
2A, 10A, 4C, 8C, 4D, 5D, 6D, 7D, 8D, 5E, 6E, 7E, 6F, 6G, 6H, 6J,
Power supply.
6K, 5L, 6L, 7L, 4M, 8M, 4N, 8N
11H
10R, 11R, 2R
1R
Output driver impedance control.
IEEE 1149.1 test inputs (1.8V LVTTL lev-
els).
IEEE 1149.1 test output (1.8V LVTTL level).
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.
F
05/08/09
3
36 Mb (1M x 36 & 2M x 18)
DDR-II (Burst of 2) CIO Synchronous SRAMs
I
®
Block Diagram
36 (or 18)
Data
Reg
Add Reg &
Burst
Control
36 (or 18)
Write Driver
Output Select
Write/Read Decode
36
(or 18)
72
(or 36)
Output Driver
Output Reg
Address
A0
19 (or 20)
19 (or 20)
36 (or 18)
DQ (Data-Out
& Data-In)
CQ, CQ
(Echo Clock Out)
LD
R/W
BW
x
K
K
C
C
4 (or 2)
Control
Logic
1M x 36
(2M x 18)
Memory
Array
Clock
Gen
Select Output Control
SRAM Features
Read Operations
The SRAM operates continuously in a burst-of-two mode. Read cycles are started by registering R/W in
active high state at the rising edge of the K clock. A second set of clocks, C and C, are used to control the
timing to the outputs. A set of free-running echo clocks, CQ and CQ, are produced internally with timings
identical to the data-outs. The echo clocks can be used as data capture clocks by the receiver device.
When the C and C clocks are connected high, the K and K clocks assume the function of those clocks. In this
case, the data corresponding to the first address is clocked 1.5 cycles later by the rising edge of the K clock.
The data corresponding to the second burst is clocked 2 cycles later by the following rising edge of the K
clock.
Whenever LD is low, a new address is registered at the rising edge of the K clock. A NOP operation (LD is
high) does not terminate the previous read. The output drivers disable automatically to a high state.
Write Operations
Write operations can also be initiated at every rising edge of the K clock whenever R/W is low. The write
address is also registered at that time. When the address needs to change, LD needs to be low simulta-
neously to be registered by the rising edge of K. Again, the write always occurs in bursts of two.
Because of its common I/O architecture, the data bus must be tri-stated at least one cycle before the new
data-in is presented at the DQ bus.
The write data is provided in a ‘late write’ mode; that is, the data-in corresponding to the first address of the
burst, is presented one cycle later or at the rising edge of the next K clock. The data-in corresponding to the
second write burst address follows next, registered by the rising edge of K.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.
F
05/08/09
Sense Amps
36 Mb (1M x 36 & 2M x 18)
DDR-II (Burst of 2) CIO Synchronous SRAMs
I
®
The data-in provided for writing is initially kept in write buffers. The information on these buffers is written into
the array on the following write cycle. A read cycle to the last write address produces data from the write
buffers. Similarly, a read address followed by the same write address produces the latest write data. The
SRAM maintains data coherency.
During a write, the byte writes independently control which byte of any of the two burst addresses is written
(see
X18/X36 Write Truth Tables
on page
9
and
Timing Reference Diagram for Truth Table
on page
8).
Whenever a write is disabled (R/W is high at the rising edge of K), data is not written into the memory.
RQ Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V
SS
to enable the SRAM
to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance
driven by the SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range
of RQ to guarantee impedance matching is between 175Ω and 350Ω, with the tolerance described in
Programmable Impedance Output Driver DC Electrical Characteristics
on page
13.
The RQ resistor should
be placed less than two inches away from the ZQ ball on the SRAM module. The capacitance of the loaded
ZQ trace must be less than 3 pF.
The ZQ pin can also be directly connected to V
DDQ
to obtain a minimum impedance setting. ZQ must never
be connected to V
SS
.
Programmable Impedance and Power-Up Requirements
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by
drifts in supply voltage and temperature. At power-up, the driver impedance is in the middle of allowable
impedances values. The final impedance value is achieved within 1024 clock cycles.
Clock Consideration
This device uses an internal DLL for maximum output data valid window. It can be placed in a stopped-clock
mode to minimize power and requires only 1024 cycles to restart.
No clocks can be issued until V
DD
reaches its allowable operating range.
Single Clock Mode
This device can be also operated in single-clock mode. In this case, C and C are both connected high at
power-up and must never change. Under this condition, K and K will control the output timings.
Either clock pair must have both polarities switching and must never connect to V
REF
, as they are not differ-
ential clocks
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.
F
05/08/09
5
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