24AA64/24LC64
64K I
2
C
™
Serial EEPROM
Device Selection Table
Part
Number
24AA64
24LC64
V
CC
Range
1.8-5.5
2.5-5.5
Max. Clock
Frequency
400 kHz
(1)
400 kHz
Temp.
Ranges
I
I, E
Description:
The Microchip Technology Inc. 24AA64/24LC64
(24XX64*) is a 64 Kbit Electrically Erasable PROM.
The device is organized as a single block of 8K x 8-bit
memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.8V, with standby
and active currents of only 1
μA
and 1 mA,
respectively. It has been developed for advanced, low-
power applications such as personal communications
or data acquisition. The 24XX64 also has a page write
capability for up to 32 bytes of data. Functional address
lines allow up to eight devices on the same bus, for up
to 512 Kbits address space. The 24XX64 is available in
the standard 8-pin PDIP, surface mount SOIC, TSSOP
and MSOP packages.
Note 1:
100 kHz for V
CC
<2.5V
Features:
• Single-supply with operation down to 1.8V
• Low-power CMOS technology:
- 1 mA active current, typical
- 1
μA
standby current (max.) (I-temp)
• Organized as a single block of 8K bytes (64K bit)
• 2-wire serial interface bus, I
2
C™ compatible
• Cascadable for up to eight devices
• Schmitt Trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz (24AA64) and 400 kHz (24LC64)
compatibility
• Self-timed write cycle (including auto-erase)
• Page write buffer for up to 32 bytes
• Hardware write-protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
• 1,000,000 erase/write cycles
• Data retention > 200 years
• 8-lead PDIP, SOIC, TSSOP, DFN and MSOP
packages
• Pb-free finish available
• Available temperature ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Package Types
PDIP, MSOP
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
A0
A1
A2
SOIC, TSSOP
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
SDA V
SS
ROTATED TSSOP
DFN
WP
Vcc
A0
A1
1
2
3
4
8
7
6
5
SCL
SDA
Vss
A2
A0 1
A1 2
A2 3
V
SS
4
8 V
CC
7 WP
6 SCL
5 SDA
Block Diagram
WP
HV
Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
Page
Latches
I/O
SCL
YDEC
SDA
V
CC
V
SS
* 24XX64 is used in this document as a generic part
number for the 24AA64/24LC64 devices.
Sense Amp.
R/W Control
©
2005 Microchip Technology Inc.
DS21189K-page 1
24AA64/24LC64
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.3V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins
......................................................................................................................................................≥
4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Industrial (I):
T
A
= -40°C to +85°C, V
CC
= +1.8V to +5.5V
Automotive (E): T
A
= -40°C to +125°C, V
CC
= +2.5V to +5.5V
Min.
—
DC CHARACTERISTICS
Param.
No.
Sym.
—
D1
D2
D3
V
IH
V
IL
V
HYS
Characteristic
A0, A1, A2, WP, SCL
and SDA pins
High-level input voltage
Low-level input voltage
Hysteresis of Schmitt
Trigger inputs (SDA,
SCL pins)
Low-level output voltage
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
Typ.
—
—
—
—
Max.
—
—
0.3 V
CC
0.2 V
CC
—
Units
—
V
V
V
V
—
—
Conditions
0.7 V
CC
—
0.05 V
CC
V
CC
≥
2.5V
V
CC
<
2.5V
V
CC
≥
2.5V
(Note 1)
D4
D5
D6
D7
D8
D9
D10
V
OL
I
LI
I
LO
C
IN
,
C
OUT
I
CC
read
I
CCS
—
—
—
—
—
—
—
—
—
—
—
—
0.1
0.05
.01
—
0.40
±1
±1
10
3
400
1
5
V
μA
μA
pF
mA
μA
μA
μA
I
OL
= 3.0 mA @ V
CC
= 4.5V
I
OL
= 2.1 mA @ V
CC
= 2.5V
V
IN
= V
SS
or V
CC
, WP = V
SS
V
IN
= V
SS
or V
CC
, WP = V
CC
V
OUT
= V
SS
or V
CC
V
CC
= 5.0V
(Note 1)
T
A
= 25°C, F
CLK
= 1 MHz
V
CC
= 5.5V, SCL = 400 kHz
Industrial
Automotive
SDA = SCL = V
CC
A0, A1, A2, WP = V
SS
I
CC
write
Operating current
Standby current
Note 1:
2:
This parameter is periodically sampled and not 100% tested.
Typical measurements taken at room temperature.
DS21189K-page 2
©
2005 Microchip Technology Inc.
24AA64/24LC64
TABLE 1-2:
AC CHARACTERISTICS
Industrial (I):
Automotive (E):
Characteristic
Clock Frequency
Clock High Time
Clock Low Time
SDA and SCL Rise Time
(Note 1)
SDA and SCL Fall Time
Start Condition Hold Time
Start Condition Setup Time
Data Input Hold Time
Data Input Setup Time
Stop Condition Setup Time
WP Setup Time
WP Hold Time
Output Valid from Clock
(Note 2)
Bus free time: Time the bus
must be free before a new
transmission can start
Output Fall Time from V
IH
Minimum to V
IL
Maximum
Input Filter Spike Suppression
(SDA and SCL pins)
Write Cycle Time (byte or
page)
Endurance
Min.
—
—
600
4000
1300
4700
—
—
—
600
4000
600
4700
0
100
250
600
4000
600
4000
1300
4700
—
—
1300
4700
20+0.1C
B
—
—
—
1M
Max.
400
100
—
—
—
—
300
1000
300
—
—
—
—
—
—
—
—
—
—
—
—
—
900
3500
—
—
250
250
50
5
—
T
A
= -40°C to +85°C, V
CC
= +1.8V to +5.5V
T
A
= -40°C to +125°C, V
CC
= +2.5V to +5.5V
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
2.5V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
<
2.5V
(24AA64)
2.5V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
<
2.5V
(24AA64)
2.5V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
<
2.5V
(24AA64)
2.5V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
<
2.5V
(24AA64)
(Note 1)
2.5V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
<
2.5V
(24AA64)
2.5V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
<
2.5V
(24AA64)
(Note 2)
2.5V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
<
2.5V
(24AA64)
2.5V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
<
2.5V
(24AA64)
2.5V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
<
2.5V
(24AA64)
2.5V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
<
2.5V
(24AA64)
2.5V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
<
2.5V
(24AA64)
2.5V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
<
2.5V
(24AA64)
2.5V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
<
2.5V
(24AA64)
(Notes 1 and 3)
—
AC CHARACTERISTICS
Param.
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Sym.
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
SU
:
WP
T
HD
:
WP
T
AA
T
BUF
15
16
17
18
Note 1:
2:
3:
4:
T
OF
T
SP
T
WC
—
ns
ns
ms
cycles 25°C,
(Note 4)
Not 100% tested. C
B
= total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a
T
I
specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.microchip.com.
©
2005 Microchip Technology Inc.
DS21189K-page 3
24AA64/24LC64
FIGURE 1-1:
BUS TIMING DATA
5
2
D4
4
SCL
SDA
IN
7
6
16
3
8
9
10
13
SDA
OUT
(protected)
(unprotected)
14
WP
11
12
DS21189K-page 4
©
2005 Microchip Technology Inc.
24AA64/24LC64
2.0
FUNCTIONAL DESCRIPTION
3.4
Data Valid (D)
The 24XX64 supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX64 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between Start and Stop conditions is
determined by the master device and is, theoretically,
unlimited (although only the last thirty two will be stored
when doing a write operation). When an overwrite does
occur, it will replace data in a first-in first-out (FIFO)
fashion.
3.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus
is not busy
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
Note:
The 24XX64 does not generate any
Acknowledge
bits
if
an
internal
programming cycle is in progress.
3.1
Bus Not Busy (A)
Both data and clock lines remain high.
3.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX64) will leave the data line
high to enable the master to generate the Stop
condition.
FIGURE 3-1:
(A)
SCL
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D)
(D)
(C)
(A)
SDA
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
©
2005 Microchip Technology Inc.
DS21189K-page 5
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