Programmable System-on-Chip (PSoC )
General Description
PSoC
®
4: PSoC 4000 Family
Datasheet
®
PSoC
®
4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
ARM
®
Cortex™-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The
PSoC 4000 product family is the smallest member of the PSoC 4 platform architecture. It is a combination of a microcontroller with
standard communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, and
general-purpose analog. PSoC 4000 products will be fully upward compatible with members of the PSoC 4 platform for new applica-
tions and design needs.
Features
32-bit MCU Subsystem
■
■
■
Timing and Pulse-Width Modulation
■
■
■
16-MHz ARM Cortex-M0 CPU
Up to 16 KB of flash with Read Accelerator
Up to 2 KB of SRAM
One 16-bit timer/counter/pulse-width modulator (TCPWM)
block
Center-aligned, Edge, and Pseudo-Random modes
Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
Programmable Analog
■
■
Two current DACs (IDACs) for general-purpose or capacitive
sensing applications
One low-power comparator with internal reference
Up to 20 Programmable GPIO Pins
■
■
■
Low Power 1.71-V to 5.5-V operation
■
28-pin SSOP, 24-pin QFN, 16-pin SOIC, 16-pin QFN, 16 ball
WLCSP, and 8-pin SOIC packages
GPIO pins on Ports 0, 1, and 2 can be CapSense or have other
functions
Drive modes, strengths, and slew rates are programmable
Deep Sleep mode with wake-up on interrupt and I
2
C address
detect
Capacitive Sensing
■
■
■
Cypress CapSense Sigma-Delta (CSD) provides best-in-class
signal-to-noise ratio (SNR) and water tolerance
Cypress-supplied software component makes capacitive
sensing design easy
Automatic hardware tuning (SmartSense™) over a sensor
range of 5 pF to 45 pF
PSoC Creator Design Environment
■
Integrated Development Environment (IDE) provides
schematic design entry and build (with analog and digital
automatic routing)
Applications Programming Interface (API) component for all
fixed-function and programmable peripherals
■
Serial Communication
■
Industry-Standard Tool Compatibility
■
Multi-master I
2
C block with the ability to do address matching
during Deep Sleep and generate a wake-up on match
After schematic entry, development can be done with
ARM-based industry-standard development tools
Cypress Semiconductor Corporation
Document Number: 001-89638 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 24, 2017
PSoC
®
4: PSoC 4000 Family
Datasheet
More Information
Cypress provides a wealth of data at
www.cypress.com
to help you to select the right PSoC device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP.
Following is an abbreviated list for PSoC 4:
■
■
■
Overview:
PSoC Portfolio, PSoC Roadmap
Product Selectors:
PSoC 1, PSoC 3, PSoC 4, PSoC 5LP
In addition, PSoC Creator includes a device selection tool.
Application notes: Cypress offers a large number of PSoC
application notes covering a broad range of topics, from basic
to advanced level. Recommended application notes for getting
started with PSoC 4 are:
❐
AN79953:
Getting Started With PSoC 4
❐
AN88619:
PSoC 4 Hardware Design Considerations
❐
AN86439:
Using PSoC 4 GPIO Pins
❐
AN57821:
Mixed Signal Circuit Board Layout
❐
AN81623:
Digital Design Best Practices
AN73854:
Introduction To Bootloaders
❐
AN89610:
ARM Cortex Code Optimization
❐
■
Technical Reference Manual (TRM) is in two documents:
❐
Architecture TRM
details each PSoC 4 functional block.
❐
Registers TRM
describes each of the PSoC 4 registers.
Development Kits:
❐
CY8CKIT-040, PSoC 4000 Pioneer Kit, is an easy-to-use and
inexpensive development platform with debugging capability.
This kit includes connectors for Arduino™ compatible shields
and Digilent
®
Pmod™ daughter cards.
❐
The MiniProg3 device provides an interface for flash
programming and debug.
■
PSoC Creator
PSoC Creator
is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100
pre-verified, production-ready PSoC Components; see the
list of component datasheets.
With PSoC Creator, you can:
3. Configure components using the configuration tools
1. Drag and drop component icons to build your hardware
system design in the main design workspace
4. Explore the library of 100+ components
2. Codesign your application firmware with the PSoC hardware,
5. Review component datasheets
using the PSoC Creator IDE C compiler
Figure 1. Example Project in PSoC Creator
1
2
3
5
5
4
Document Number: 001-89638 Rev. *H
Page 2 of 35
PSoC
®
4: PSoC 4000 Family
Datasheet
Contents
Functional Definition ........................................................ 5
CPU and Memory Subsystem ..................................... 5
System Resources ...................................................... 5
Analog Blocks .............................................................. 6
Fixed Function Digital .................................................. 6
GPIO ........................................................................... 6
Special Function Peripherals ....................................... 6
Pinouts .............................................................................. 7
Power ............................................................................... 12
Unregulated External Supply ..................................... 12
Regulated External Supply ........................................ 12
Development Support .................................................... 13
Documentation .......................................................... 13
Online ........................................................................ 13
Tools .......................................................................... 13
Electrical Specifications ................................................ 14
Absolute Maximum Ratings ...................................... 14
Device Level Specifications ....................................... 14
Analog Peripherals .................................................... 17
Digital Peripherals ..................................................... 19
Memory ..................................................................... 20
System Resources .................................................... 20
Ordering Information ...................................................... 23
Part Numbering Conventions .................................... 23
Packaging ........................................................................ 25
Package Outline Drawings ........................................ 26
Acronyms ........................................................................ 31
Document Conventions ................................................. 33
Units of Measure ....................................................... 33
Revision History ............................................................. 34
Sales, Solutions, and Legal Information ...................... 35
Worldwide Sales and Design Support ....................... 35
Products .................................................................... 35
PSoC® Solutions ...................................................... 35
Cypress Developer Community ................................. 35
Technical Support ..................................................... 35
Document Number: 001-89638 Rev. *H
Page 3 of 35
PSoC
®
4: PSoC 4000 Family
Datasheet
Figure 2. Block Diagram
CPU Subsystem
PSoC 4000
32-bit
SWD/TC
SPCIF
Cortex
M0
16 MHz
MUL
NVIC, IRQMX
Flash
16 KB
Read Accelerator
SRAM
2 KB
SRAM Controller
ROM
4 KB
ROM Controller
AHB- Lite
System Resources
Lite
Power
Sleep Control
WIC
POR
REF
PWRSYS
Clock
Clock Control
WDT
IMO
ILO
Reset
Reset Control
XRES
Test
DFT Logic
DFT Analog
System Interconnect (Single/Multi Layer AHB)
Peripherals
PCLK
Peripheral Interconnect (MMIO)
1x TCPWM
1x SCB-
I2C
IOSS GPIO
(4x ports)
Power Modes
Active/ Sleep
Deep Sleep
High Speed I/O Matrix
20 x GPIOs
I/O Subsystem
PSoC 4000 devices include extensive support for programming,
testing, debugging, and tracing both hardware and firmware.
The ARM Serial-Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE provides fully integrated programming
and debug support for the PSoC 4000 devices. The SWD
interface is fully compatible with industry-standard third-party
tools. The PSoC 4000 family provides a level of security not
possible with multi-chip application solutions or with microcon-
trollers. It has the following advantages:
■
■
■
The debug circuits are enabled by default and can only be
disabled in firmware. If they are not enabled, the only way to
re-enable them is to erase the entire device, clear flash
protection, and reprogram the device with new firmware that
enables debugging.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. All programming, debug, and test interfaces are
disabled when maximum device security is enabled. Therefore,
PSoC 4000, with device security enabled, may not be returned
for failure analysis. This is a trade-off the PSoC 4000 allows the
customer to make.
Allows disabling of debug features
Robust flash protection
Allows customer-proprietary functionality to be implemented in
on-chip programmable blocks
Page 4 of 35
Document Number: 001-89638 Rev. *H
CapSense
PSoC
®
4: PSoC 4000 Family
Datasheet
Functional Definition
CPU and Memory Subsystem
CPU
The Cortex-M0 CPU in the PSoC 4000 is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating. Most instructions are 16 bits in length and
the CPU executes a subset of the Thumb-2 instruction set. This
enables fully compatible, binary, upward migration of the code to
higher performance processors, such as the Cortex-M3 and M4.
It includes a nested vectored interrupt controller (NVIC) block
with eight interrupt inputs and also includes a Wakeup Interrupt
Controller (WIC). The WIC can wake the processor from the
Deep Sleep mode, allowing power to be switched off to the main
processor when the chip is in the Deep Sleep mode. The CPU
subsystem also includes a 24-bit timer called SYSTICK, which
can generate an interrupt.
The CPU also includes a debug interface, the serial wire debug
(SWD) interface, which is a 2-wire form of JTAG. The debug
configuration used for PSoC 4000 has four breakpoint (address)
comparators and two watchpoint (data) comparators.
Flash
The PSoC 4000 device has a flash module with a flash accel-
erator, tightly coupled to the CPU to improve average access
times from the flash block. The low-power flash block is designed
to deliver zero wait-state (WS) access time at 16 MHz.
SRAM
Two KB of SRAM are provided with zero wait-state access at
16 MHz.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
Clock System
The PSoC 4000 clock system is responsible for providing clocks
to all subsystems that require clocks and for switching between
different clock sources without glitching. In addition, the clock
system ensures that there are no metastable conditions.
The clock system for the PSoC 4000 consists of the internal main
oscillator (IMO) and the internal low-frequency oscillator (ILO)
and provision for an external clock.
Figure 3. PSoC 4000 MCU Clocking Architecture
IMO
F
CPU
Divide By
2,4,8
External Clock
( connects to GPIO pin P 0.4 )
The F
CPU
signal can be divided down to generate synchronous
clocks for the analog and digital peripherals. There are four clock
dividers for the PSoC 4000, each with 16-bit divide capability The
16-bit capability allows flexible generation of fine-grained
frequency values and is fully supported in PSoC Creator.
IMO Clock Source
The IMO is the primary source of internal clocking in the
PSoC 4000. It is trimmed during testing to achieve the specified
accuracy.The IMO default frequency is 24 MHz and it can be
adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO
tolerance with Cypress-provided calibration settings is ±2% (24
and 32 MHz).
ILO Clock Source
The ILO is a very low power, 40-kHz oscillator, which is primarily
used to generate clocks for the watchdog timer (WDT) and
peripheral operation in Deep Sleep mode. ILO-driven counters
can be calibrated to the IMO to improve accuracy.
Watchdog Timer
A watchdog timer is implemented in the clock block running from
the ILO; this allows watchdog operation during Deep Sleep and
generates a watchdog reset if not serviced before the set timeout
occurs. The watchdog reset is recorded in a Reset Cause
register, which is firmware readable.
Reset
The PSoC 4000 can be reset from a variety of sources including
a software reset. Reset events are asynchronous and guarantee
reversion to a known state. The reset cause is recorded in a
register, which is sticky through reset and allows software to
determine the cause of the reset. An XRES pin is reserved for
external reset on the 24-pin package. An internal POR is
provided on the 16-pin and 8-pin packages. The XRES pin has
an internal pull-up resistor that is always enabled. Reset is Active
Low.
Voltage Reference
The PSoC 4000 reference system generates all internally
required references. A 1.2-V voltage reference is provided for the
comparator. The IDACs are based on a ±5% reference.
System Resources
Power System
The power system is described in detail in the section on
Power
on page 12.
It provides an assurance that voltage levels are as
required for each respective mode and either delays mode entry
(for example, on power-on reset (POR)) until voltage levels are
as required for proper functionality, or generates resets (for
example, on brown-out detection). The PSoC 4000 operates
with a single external supply over the range of either 1.8 V ±5%
(externally regulated) or 1.8 to 5.5 V (internally regulated) and
has three different power modes, transitions between which are
managed by the power system. The PSoC 4000 provides Active,
Sleep, and Deep Sleep low-power modes.
All subsystems are operational in Active mode. The CPU
subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep
mode, while all peripherals and interrupts are active with instan-
taneous wake-up on a wake-up event. In Deep Sleep mode, the
high-speed clock and associated circuitry is switched off;
wake-up from this mode takes 35 µS.
Document Number: 001-89638 Rev. *H
Page 5 of 35
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