NB100ELT23L
3.3V Dual Differential
LVPECL/LVDS to LVTTL
Translator
The NB100ELT23L is a dual differential LVPECL/LVDS to LVTTL
translator. Because LVPECL (Positive ECL) or LVDS levels are used,
only +3.3 V and ground are required. The small outline 8-lead package
and the dual gate design of the ELT23L makes it ideal for applications
which require the translation of a clock and a data signal.
The ELT23L is available in only the ECL 100K standard. Since
there are no LVPECL outputs or an external V
BB
reference, the
ELT23L does not require both ECL standard versions. The LVPECL
inputs are differential. Therefore, the NB100ELT23L can accept any
standard differential LVPECL/LVDS input referenced from a V
CC
of
+3.3 V.
Features
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MARKING
DIAGRAMS*
8
8
1
SOIC−8
D SUFFIX
CASE 751
1
KT23L
ALYW
G
•
•
•
•
•
8
8
1
TSSOP−8
DT SUFFIX
CASE 948R
1
K23L
ALYWG
G
2.1 ns Typical Propagation Delay
Maximum Operating Frequency > 160 MHz
24 mA LVTTL Outputs
Operating Range: V
CC
= 3.0 V to 3.6 V with GND = 0 V
Pb−Free Packages are Available
DFN8
MN SUFFIX
CASE 506AA
1
A
L
Y
W
M
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
©
Semiconductor Components Industries, LLC, 2010
November, 2010
−
Rev. 11
1
Publication Order Number:
NB100ELT23L/D
6F M
G
G
4
NB100ELT23L
Table 1. PIN DESCRIPTION
D0
1
8
V
CC
PIN
Q0, Q1
D0
2
LVPECL
D1
3
LVTTL
6
Q1
7
Q0
D0*, D1*
D0**, D1**
V
CC
GND
EP
LVTTL Outputs
Differential LVPECL Inputs
Positive Supply
Ground
(DFN8 only) Thermal exposed pad must be con-
nected to a sufficient thermal conduit. Electric-
ally connect to the most negative supply (GND)
or leave unconnected, floating open.
FUNCTION
D1
4
5
GND
*Pins will default to V
CC
/2 when left open. If connected to a
common termination voltage under no signal conditions, then the
device will be susceptible to self−oscillation.
**Pins will default to 2/3 V
CC
when left open. If connected to a
common termination voltage under no signal conditions, then the
device will be susceptible to self−oscillation. See AND8020,
Section 6 for options.
Figure 1. 8−Lead Pinout
(Top View)
and
Logic Diagram
Table 2. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
D
D
Value
50 kW
75 kW
50 kW
> 1.5 kV
> 100 V
> 2 kV
Level 1
UL 94 V−0 @ 1.25 in
91 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
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2
NB100ELT23L
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
I
I
out
T
A
T
stg
q
JA
q
JC
q
JA
q
JC
q
JA
T
sol
q
JC
Power Supply
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Wave Solder
Pb
Pb−Free
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
(Note 2)
DFN8
SO−8
SO−8
SO−8
TSSOP−8
TSSOP−8
TSSOP−8
DFN8
DFN8
Parameter
Condition 1
GND = 0 V
GND = 0 V
Continuous
Surge
V
I
≤
V
CC
Condition 2
Rating
3.8
3.8
50
100
−40
to +85
−65
to +150
190
130
41 to 44
185
140
41 to 44
129
84
265
265
35 to 40
Unit
V
V
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C
°C/W
Thermal Resistance (Junction−to−Case)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power)
Table 4. PECL DC CHARACTERISTICS
V
CC
= 3.3 V, GND = 0 V (Note 3)
−40°C
Symbol
I
CCH
I
CCL
V
IH
V
IL
V
IHCMR
I
IH
I
IL
Characteristic
Power Supply Current (Outputs set to HIGH)
Power Supply Current (Outputs set to LOW)
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage Common Mode Range
(Note 4)
Input HIGH Current
Input LOW Current
−150
Min
10
15
2075
1355
1.2
Typ
23
26
Max
30
35
2420
1675
3.3
150
−150
Min
10
15
2075
1355
1.2
25°C
Typ
23
26
Max
30
35
2420
1675
3.3
150
−150
Min
10
15
2075
1355
1.2
85°C
Typ
24
27
Max
30
35
2420
1675
3.3
150
Unit
mA
mA
mV
mV
V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. All values vary 1:1 with V
CC
.
4. V
IHCMR
minimum varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the
differential input signal.
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3
NB100ELT23L
Table 5. TTL DC CHARACTERISTICS
V
CC
= 3.3 V, GND = 0.0 V, T
A
=
−40°C
to 85°C
Symbol
V
OH
V
OL
I
OS
Characteristic
Output HIGH Voltage
Output LOW Voltage
Output Short Circuit Current
Condition
I
OH
=
−3.0
mA
I
OL
= 24 mA
−180
Min
2.4
0.5
−50
Typ
Max
Unit
V
V
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 6. AC CHARACTERISTICS
V
CC
= 3.3 V
$
5%, GND = 0.0 V (Note 5)
−40°C
Symbol
f
max
t
PLH
,
t
PHL
t
SK+ +
t
SK−
−
t
SKPP
t
JITTER
V
PP
t
r
t
f
Characteristic
Maximum Frequency
Propagation Delay to Output Differential
(Note 6)
C
L
= 20 pF
Output−to−Output Skew++
Output−to−Output Skew−
−
Part−to−Part Skew (Note 7)
Random Clock Jitter (RMS)
Input Voltage Swing
(Differential Configuration)
Output Rise/Fall Times
C
L
= 20 pF (0.8 V to 2.0 V)
150
700
300
6.0
800
900
Min
160
1.55
1.9
2.95
60
25
500
20
1200
1700
1250
150
700
300
6.0
800
900
Typ
Max
Min
160
1.55
1.9
2.95
60
25
500
20
1200
1700
1250
150
700
300
6.0
800
900
25°C
Typ
Max
Min
160
1.55
1.9
3.25
60
25
500
20
1200
1700
1250
85°C
Typ
Max
Unit
MHz
ns
ps
ps
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 500
W
to GND, C
L
= 20 pF.
6. Reference (V
CC
= 3.3 V
±
5%; GND = 0 V).
7. Skews are measured between outputs under identical conditions.
APPLICATION
TTL RECEIVER
CHARACTERISTIC TEST
*C
L
includes
fixture
capacitance
C
L
*
R
L
AC TEST LOAD
GND
Figure 2. TTL Output Loading Used for Device Evaluation
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4
NB100ELT23L
ORDERING INFORMATION
Device
NB100ELT23LD
NB100ELT23LDG
NB100ELT23LDR2
NB100ELT23LDR2G
NB100ELT23LDT
NB100ELT23LDTG
NB100ELT23LDTR2
NB100ELT23LDTR2G
NB100ELT23LMNR4
NB100ELT23LMNR4G
Package
SO−8
SO−8
(Pb−Free)
SO−8
SO−8
(Pb−Free)
TSSOP−8
TSSOP−8
(Pb−Free)
TSSOP−8
TSSOP−8
(Pb−Free)
DFN8
DFN8
(Pb−Free)
Shipping
†
98 Units / Rail
98 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
100 Units / Rail
100 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
1000 / Tape & Reel
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
ECL Clock Distribution Techniques
−
Designing with PECL (ECL at +5.0 V)
−
ECLinPSt I/O SPiCE Modeling Kit
−
Metastability and the ECLinPS Family
−
Interfacing Between LVDS and ECL
−
The ECL Translator Guide
−
Odd Number Counters Design
−
Marking and Date Codes
−
Termination of ECL Logic Devices
−
Interfacing with ECLinPS
−
AC Characteristics of ECL Devices
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