MB15F73UL
ASSP Dual Serial Input PLL Frequency
Synthesizer Datasheet
Description
The Cypress Semiconductor MB15F73UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2250 MHz and a
600-MHz prescalers. A 64/65 or a 128/129 for the 2250-MHz prescaler, and a 8/9 or a 16/17 for the 600 MHz prescaler can be selected
for the prescaler that enables pulse swallow operation.
The BiCMOS process is used, as a result a supply current is typically 3.2 mA at 2.7 V. The supply voltage range is from 2.4 V to 3.6
V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA selectable by serial date. The data format is
the same as the previous one MB15F03SL and MB15F73SP. Fast locking is achieved for adopting the new circuit.
Features
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23-bit shift register
Serial input binary 14-bit programmable reference divider:
R = 3 to 16,383
Serial input programmable divider consisting of:
❐
Binary 7-bit swallow counter: 0 to 127
❐
Binary 11-bit programmable counter: 3 to 2,047
Built-in high-speed tuning, low-noise phase comparator,
current-switching type constant current circuit
On-chip phase control for phase comparator
On-chip phase comparator for fast lock and low noise
Built-in digital locking detector circuit to detect PLL locking and
unlocking.
Operating temperature: Ta = –40 °C to +85 °C
High frequency operation
❐
RF synthesizer: 2250 MHz Max
❐
IF synthesizer: 600 MHz Max
Low power supply voltage: V
CC
= 2.4 V to 3.6 V
Ultra low power supply current: I
CC
= 3.2 mA Typ
(V
CC
= Vp = 2.7 V, SW
IF
= SW
RF
= 0, Ta = +25 °C, in IF, RF locking
state)
Direct power saving function: Power supply current in power
saving mode
❐
Typ 0.1
A (V
CC
= Vp = 2.7 V, Ta = +25 °C)
❐
Max 10
A (V
CC
= Vp = 2.7 V)
Software selectable charge pump current : 1.5 mA/6.0 mA Typ
Dual modulus prescaler: 2250-MHz prescaler (64/65 or 128/
129) /600 MHz prescaler (8/9 or 16/17)
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Cypress Semiconductor Corporation
Document Number: 002-08480 Rev. *A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 5, 2017
MB15F73UL
Block Diagram
V
CCIF
GND
IF
(4) 6
5 (3)
Vp
IF
8 (6)
SW
IF
PS
IF
7
(5)
LDS
FC
IF
Intermittent
mode control
(IF-PLL)
3 bit latch
7 bit latch
11 bit latch
Phase
comp.
(IF-PLL)
Charge
pump Current
(IF-PLL) Switch
9 Do
IF
(7)
Binary 7-bit
Binary 11-bit
swallow counter programmable
(IF-PLL)
counter (IF-PLL)
fp
IF
fin
IF
3
(1)
Xfin
IF
4
(2)
Prescaler
(IF-PLL)
(8/9, 16/17)
2 bit latch
T1
T2
14 bit latch
Binary 14-bit pro-
grammable ref.
counter(IF-PLL)
fr
IF
OSC
IN
1
(19)
fr
RF
T1
OR
2 bit latch
(15)
fin
RF
17
Xfin
RF
16
(14)
Prescaler
(RF-PLL)
(64/65, 128/129)
Lock Det.
(IF-PLL)
1 bit latch
C/P setting
counter
LD
IF
Fast
lock
Tuning
AND
C/P setting
counter
Selector
T2
Binary 14-bit pro-
grammable ref.
counter (RF-PLL))
14 bit latch
1 bit latch
LD
RF
fp
RF
Lock Det.
(RF-PLL)
LD
fr
IF
fr
RF
fp
IF
fp
RF
10 LD/
(8) fout
PS
RF
13
(11)
Intermittent
mode control
(RF-PLL)
Binary 11-bit
Binary 7-bit
swallow counter programmable
counter (RF-PLL)
(RF-PLL)
Phase
comp.
(RF-PLL)
Fast lock
Tuning
Charge
Current
pump
Switch
(RF-PLL)
SW
RF
FC
RF
11 Do
RF
(9)
LDS
fp
RF
3 bit latch
7 bit latch
11 bit latch
LE 18
(16)
(17)
Data 19
Clock 20
(18)
Schmitt
circuit
Latch selector
Schmitt
circuit
Schmitt
circuit
C C
N N
1 2
23-bit shift register
2 (20)
GND
(12) 14
15 (13)
V
CCRF
GND
RF
12 (10)
Vp
RF
O: TSSOP
( ) : QFN
Document Number: 002-08480 Rev. *A
Page 2 of 29
MB15F73UL
Contents
Pin Assignments .............................................................. 4
Pin Description ................................................................. 5
Absolute Maximum Ratings ............................................ 6
Recommended Operating Conditions ............................ 6
Electrical Characteristics................................................. 7
Functional Description..................................................... 9
Pulse swallow function ................................................ 9
Serial Data Input.......................................................... 9
Shift Register Configuration ....................................... 9
Data setting ............................................................... 10
Power Saving Mode (Intermittent Mode
Control Circuit).......................................................... 12
Serial Data Input Timing............................................ 13
Phase Comparator Output Waveform .......................... 14
LD Output Logic ........................................................ 14
Test Circuit (for Measuring Input Sensitivity
fin/OSCIN)....................................................................... 15
Typical Characteristics .................................................. 16
Fin Input Sensitivity ................................................... 16
OSCIN input sensitivity.............................................. 17
RF-PLL Do output current ......................................... 18
IF-PLL Do output current........................................... 19
fin input impedance ................................................... 20
OSCIN input impedance............................................ 21
Reference Information (for Lock-up Time, Phase Noise, and
Reference Leakage)........................................................ 22
Application Example ...................................................... 24
Usage Precautions ......................................................... 25
Ordering Information..................................................... 25
Package Dimensions...................................................... 26
Document History Page ................................................. 28
Sales, Solutions, and Legal Information ...................... 29
Worldwide Sales and Design Support....................... 29
Products .................................................................... 29
PSoC® Solutions ...................................................... 29
Cypress Developer Community................................. 29
Technical Support ..................................................... 29
Document Number: 002-08480 Rev. *A
Page 3 of 29
MB15F73UL
Pin Assignments
(TSSOP-20)
Top View
(QFN-20)
Top View
OSC
IN
Clock
GND
Data
17
LE
16
15 fin
RF
14 Xfin
RF
13 GND
RF
12 V
CCRF
11 PS
RF
6
Vp
IF
7
Do
IF
8
LD/fout
9
Do
RF
10
Vp
RF
OSC
IN
GND
fin
IF
Xfin
IF
GND
IF
V
CCIF
PS
IF
Vp
IF
Do
IF
LD/fout
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Clock
Data
LE
fin
RF
Xfin
RF
GND
RF
V
CCRF
PS
RF
Vp
RF
Do
RF
20
fin
IF
Xfin
IF
GND
IF
V
CC
IF
PS
IF
1
2
3
4
5
19
18
(FPT-20P-M06)
(LCC-20P-M63)
Document Number: 002-08480 Rev. *A
Page 4 of 29
MB15F73UL
Pin Description
Pin no.
TSSOP
1
2
3
4
5
6
7
QFN
19
20
1
2
3
4
5
Pin name
OSC
IN
GND
fin
IF
Xfin
IF
GND
IF
V
CCIF
PS
IF
I/O
I
–
I
I
–
–
I
Descriptions
The programmable reference divider input pin. TCXO should be connected with an
AC coupling capacitor.
Ground pin for OSC input buffer and the shift register circuit.
Prescaler input pin for the IF-PLL.
Connection to an external VCO should be via AC coupling.
Prescaler complimentary input for the IF-PLL section.
This pin should be grounded via a capacitor.
Ground pin for the IF-PLL section.
Power supply voltage input pin for the IF-PLL section (except for the charge pump
circuit), the shift register, and the oscillator input buffer.
Power saving mode control for the IF-PLL section. This pin must be set at “L” when
the power supply is started up. (Open is prohibited.)
PS
IF
= “H”; Normal mode / PS
IF
= “L”; Power saving mode
Power supply voltage input pin for the IF-PLL charge pump.
Charge pump output for the IF-PLL section.
Lock detect signal output (LD) /phase comparator monitoring
output (fout) pin.The output signal is selected by LDS bit in the serial data.
LDS bit = “H”; outputs fout signal / LDS bit = “L”; outputs LD signal
Charge pump output for the RF-PLL section.
Power supply voltage input pin for the RF-PLL charge pump.
Power saving mode control for the RF-PLL section. This pin must be set at “L” when
the power supply is started up. (Open is prohibited.)
PS
RF
= “H”; Normal mode / PS
RF
= “L”; Power saving mode
Power supply voltage input pin for the RF-PLL section (except for the charge pump
circuit)
Ground pin for the RF-PLL section
Prescaler complimentary input pin for the RF-PLL section.
This pin should be grounded via a capacitor.
Prescaler input pin for the RF-PLL.
Connection to an external VCO should be via AC coupling.
Load enable signal input pin (with the schmitt trigger circuit)
When LE is set “H”, data in the shift register is transferred to the
corresponding latch according to the control bit in the serial data.
Serial data input pin (with the schmitt trigger circuit)
Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter, RF-
ref. counter, RF-prog. counter) according to the control bit in
the serial data.
Clock input pin for the 23-bit shift register (with the schmitt trigger circuit)
One bit of data is shifted into the shift register on a rising edge of the clock.
8
9
10
6
7
8
Vp
IF
D
OIF
LD/fout
–
O
O
11
12
13
9
10
11
D
ORF
Vp
RF
PS
RF
O
–
I
14
15
16
17
18
12
13
14
15
16
V
CCRF
GND
RF
Xfin
RF
fin
RF
LE
–
–
I
I
I
19
17
Data
I
20
18
Clock
I
Document Number: 002-08480 Rev. *A
Page 5 of 29
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