response with minimum output capacitance and tight ripple
regulation at very light load. The part is stable with any
capacitor type and no ESR network is required for loop
stability. The device also incorporates a power saving
scheme that significantly increases light load efficiency.
The regulator integrates a full protection feature set,
including output overvoltage protection (OVP), output under
voltage protection (UVP) and thermal shutdown (OTP). It
also has UVLO for input rail and internal soft-start ramp.
The SiP12110 is available in lead (Pb)-free power enhanced
3 mm x 3 mm QFN16-33G package.
• Ultrafast transient response
• Power saving scheme for increased light load efficiency
• ± 1 % accuracy of V
OUT
setting
• Cycle-by-cycle current limit
• Fully protected with OTP, SCP, UVP, OVP
• P
GOOD
indicator
• -40 °C to +125 °C operating junction temperature
• Output voltage tracking
• Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
APPLICATIONS
• Point of load regulation for low-power processors,
network processors, DSPs, FPGAs, and ASICs
• Low voltage, distributed power architectures with 5 V
or 12 V rails
• Computing, broadband, networking, LAN / WAN, optical,
test and measurement
• A/V, high density cards, storage, DSL, STB, DVR, DTV,
Industrial PC
TYPICAL APPLICATION CIRCUIT
Enable
Power good
Input = 4.5 V to 15 V
P
GOOD
V
IN
SS
V
CC
P
GND
A
GND
V
FB
COMP
R
ON
EN BOOT
V
OUT
LX
Fig. 1 - Typical Application Circuit for SiP12110
S20-0484-Rev. B, 29-Jun-2020
Document Number: 64299
1
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiP12110
www.vishay.com
Vishay Siliconix
MARKING
(LINE 2: P/N)
2110
Reference board
ORDERING INFORMATION
PART NUMBER
SiP12110DMP-T1-GE4
SiP12110DB
PACKAGE
QFN16 3 x 3
MARKING
P/N
FYWLL
Format:
Line 1: Dot
Line 2: P/N
Line 3:
Siliconix
logo + ESD
symbol
Line 4: Factory code + year code + work week code + LOT code
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL PARAMETER
V
IN
V
CC
LX
LX (AC voltage)
BOOT
A
GND
to P
GND
All logic inputs and outputs
(R
ON
, COMP, V
FB
, SS, EN, P
GOOD
)
TEMPERATURE
Max. operating junction temperature
Storage temperature
POWER DISSIPATION
Junction to ambient thermal impedance
(R
thJA
)
Maximum power dissipation
ESD PROTECTION
Electrostatic discharge protection
Human body model, JESD22-A114
2
kV
Ambient temperature = 25 °C
Ambient temperature = 100 °C
36.3
3.4
1.3
°C/W
W
-40 to +150
-65 to +150
°C
Reference to A
GND
CONDITIONS
Reference to P
GND
Reference to A
GND
Reference to P
GND
100 ns; reference to P
GND
10 ns; reference to P
GND
LIMIT
-0.3 to 16
-0.3 to 6
-1 to 16
-2 to 17
-6 to 17
-0.3 to V
IN
+ V
CC
-0.3 to 0.3
-0.3 to V
CC
+ 0.3
V
UNIT
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
S20-0484-Rev. B, 29-Jun-2020
Document Number: 64299
2
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiP12110
www.vishay.com
Vishay Siliconix
MINIMUM
4.5
4.5
0.6
TYPICAL
-
-
-
-40 to +85
-40 to +125
MAXIMUM
15
5.5
5.5
V
UNIT
RECOMMENDED OPERATING RANGE
(all voltages referenced to GND = 0 V)
ELECTRICAL PARAMETER
V
IN
V
CC
V
OUT
TEMPERATURE
Recommended ambient temperature
Operating junction temperature
°C
ELECTRICAL SPECIFICATIONS
(test condition unless otherwise specified)
PARAMETER
POWER SUPPLY
Power input voltage range
V
CC
regulator voltage
Input current
Shutdown current
V
CC
UVLO threshold
V
CC
UVLO hysteresis
CONTROLLER AND TIMING
Feedback reference
V
FB
input bias current
Transconductance
COMP source current
COMP sink current
On-time
Minimum off-time
Soft start current
POWER MOSFETS
High-side on resistance
Low-side on resistance
FAULT PROTECTIONS
Over current limit
Output OVP threshold
Output UVP threshold
Over temperature protection
POWER GOOD
Power good output threshold
Power good on resistance
Power good delay time
ENABLE THRESHOLD
Logic high level
Logic low level
Note
(1)
Tie V
CC
to V
IN
when V
IN
< 5.5 V
V
EN_H
V
EN_L
1.5
-
-
-
-
0.4
V
V
FB_RISING_VTH_OV
V
FB_FALLING_VTH_UV
R
ON_PGOOD
t
DLY_PGOOD
V
FB
rising above 0.6 V reference
V
FB
falling below 0.6 V reference
-
-
-
-
21
-12.5
30
5
-
-
60
-
%
μs
I
OCP
V
FB_OVP
V
FB_UVP
Inductor valley current
V
FB
with respect to 0.6 V reference
Rising temperature
Hysteresis
-
-
-
-
-
7.5
21
-65
160
35
-
-
-
-
-
A
%
°C
R
ON_HS
R
ON_LS
V
GS
= 5 V
-
-
45
27
67
41
m
V
FB
I
FB
g
m
I
COMP_SOURCE
I
COMP_SINK
t
ON
t
OFF_MIN.
I
SS
R
on
= 75 k
T
A
= 25 °C
T
A
= -40 °C to +85 °C
0.596
0.594
-
-
-
-
100
145
3
0.600
0.600
2
1
50
50
135
200
5
0.604
0.606
200
-
-
-
170
255
7
V
nA
mS
μA
ns
μA
V
IN
V
CC
IV
IN_NOLOAD
IV
IN_SHDN
V
CC_UVLO
V
CC_UVLO_HYS
T
A
= 25 °C, R
on
= 75 k,
Non-switching, I
O
= 0 A
EN = 0 V
V
CC
rising
Note 1
4.5
4.5
-
-
2.3
-
-
5
1.2
5
2.55
300
15
5.5
-
8
2.8
-
V
mA
μA
V
mV
SYMBOL
TEST CONDITION
V
IN
= 12 V, T
A
= -40 °C to +85 °C
LIMITS
MIN.
TYP.
MAX.
UNIT
S20-0484-Rev. B, 29-Jun-2020
Document Number: 64299
3
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiP12110
www.vishay.com
FUNCTIONAL BLOCK DIAGRAM
COMP
VCC
PGOOD
EN
VIN
BOOT
AGND
OTP
VCC
0.6 V
reference
5 μA
Soft
start
Vishay Siliconix
VCC
5V
regulator
UVLO
SS
+
+ OTA
VFB
-
VIN
+
On-time
generator
LX
Control
logic
sectionl
Anti-
XCOND
control
LX
VCC
LX
-
PWM
comparator
I
sense
I-V
converter
ZCD
RON
-
+
0.45 V
VFB
PAD
0.72 V
+
-
OV comparator
UV comparator
Current
mirror
OCP
PGND
PGND
I
sense
Fig. 2 - SiP12110 Functional Block Diagram
PIN CONFIGURATION
BOOT
13
12
11
16
P
GND
15
V
IN
V
CC
A
GND
R
ON
1
2
3
4
5
6
7
8
P
GND
14
V
IN
LX
LX
LX
P
GOOD
P
GND
10
9
COMP
V
FB
Fig. 3 - SiP12110 Pin Configuration (Top View)
PIN CONFIGURATION
PIN NUMBER
1, 16
2
3
4
5
6
7
8
9
10, 11, 12
13
14, 15, PAD
NAME
V
IN
V
CC
A
GND
R
ON
COMP
V
FB
SS
EN
P
GOOD
LX
BOOT
P
GND
FUNCTION
Input supply voltage for power MOS. V
IN
= 4.5 V to 15 V
Internal regulator output, tie V
CC
to V
IN
when V
IN
< 5.5 V
Analog ground
An external resistor between R
ON
and A
GND
sets the switching on time
Connect to an external RC network for loop compensation and droop function
Feedback voltage. 0.6 V (typ.). Use a resistor divider between V
OUT
and A
GND
to set the output voltage
An external capacitor between SS and A
GND
sets the soft start time
Enable pin. Pull enable above 1.5 V to enable and below 0.4 V to disable the part. Do not float this pin
Power good output. Open drain
Switching node, inductor connection point
Bootstrap pin - connect a capacitor of at least 100 nF from BOOT to LX to develop the floating supply
for the high-side gate drive
Power ground
S20-0484-Rev. B, 29-Jun-2020
Document Number: 64299
4
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
EN
SS
SiP12110
www.vishay.com
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
(V
IN
= 12 V, V
OUT
= 1.2 V, L = 1.5 μH, C = 3 x 22 μF, unless otherwise noted)
100
90
80
Efficiency (%)
70
60
50
40
30
20
0.0
0.6
1.2
1.8
2.4
3.0
I
OUT
(A)
3.6
4.2
4.8
5.4
6.0
V
OUT
= 1.2 V
V
OUT
= 5 V
1.6
1.2
0.8
Load Regulation (%)
0.4
0
-0.4
-0.8
-1.2
-1.6
0.0
0.6
1.2
1.8
2.4
3.0 3.6
I
OUT
(A)
4.2
4.8
5.4
6.0
V
OUT
= 1.2 V
V
OUT
= 5 V
Fig. 4 - Efficiency vs. I
OUT
1600
1400
Switching
Frequency, F
SW
(kHz)
1200
1000
800
600
400
200
0
0.0
0.6
1.2
1.8
2.4
3.0
I
OUT
(A)
3.6
4.2
4.8
5.4
6.0
V
OUT
= 5 V
V
OUT
= 1.2 V
EN Threshold Voltage, V
EN
(V)
1.6
1.4
Fig. 7 - Load Regulation vs. I
OUT
V
EN_H
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-60 -40 -20
0
20 40 60 80
Temperature (°C)
100 120 140
V
EN_L
Fig. 5 - Frequency Variation vs. I
OUT
Fig. 8 - EN Threshold vs. Temperature
CH2
CH2
CH3
CH3
CH1
CH1
Fig. 6 - Steady-State, I
OUT
= 0 A
CH1 (BRN) = LX (10 V/div), CH3 (BLU) = V
OUT
(20 mV/div),
CH2 (RED) = I
COIL
(1 A/div), Time = 10 μs/div
S20-0484-Rev. B, 29-Jun-2020
Fig. 9 - Steady-State, I
OUT
= 6 A
CH1 (BRN) = LX (10 V/div), CH3 (BLU) = V
OUT
(20 mV/div),
CH2 (RED) = I
COIL
(1 A/div), Time = 1 μs/div
Document Number: 64299
5
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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