Resistance to sulphur-bearing gas (AS version only): ASTM-B-809
Voltage proof
Volts
Note: A 0.01 Ohm addition to be added to the performance of all resistors <10 Ohms.
ΔR%
ΔR%
ΔR%
ΔR%
ΔR%
1
1
1
0.25
0.25
0.25
500
ΔR%
ΔR%
Maximum
1
0.1
Zero at 155°C
0.1
0.2
0.25
0.05
0.05
0.05
Typical
0.25
0.02
Pulse Performance Data
Pulse Performance Data
Lightning Surge
Lightning surge resistors are tested in accordance with IEC 60 115-1 using both 1.2/50µs and 10/700µs pulse shapes. 10 pulses are applied. The limit of
acceptance is a shift in resistance of less than 1% from the initial value.
2512
2010
1206
0805
0603
Lightning Surge
Lightning surge resistors are tested in
accordance with IEC 60 115-1 using
both 1.2/50µs and 10/700µs pulse shapes.
10 pulses are applied. The limit of
acceptance is a shift in resistance of less
than 1% from the initial value.
2512
2010
1206
0805
0603
General Note
TT Electronics reserves the right to make changes in product specification without notice or liability.
All information is subject to TT Electronics’ own data and is considered accurate at time of going to print.
The single impulse graph is the result of 50 impulses of rectangular shape applied at one minute intervals. The limit of acceptance was a shift in
resistance of less than 1% from the initial value.
2512
2010
1206
0805
0603
Continuous Load Due to Repetitive Pulses
The continuous load graph was obtained by applying repetitive rectangular pulses where the pulse period was adjusted so that the average
power dissipated in the resistor was equal to its rated power at 70°C. Again the limit of acceptance was a shift in resistance of less than 1% from the
initial value
2512
2010
1206
0805
0603
General Note
TT Electronics reserves the right to make changes in product specification without notice or liability.
All information is subject to TT Electronics’ own data and is considered accurate at time of going to print.
程序以前一直跑都没问题，现在出现错误：
Sat Jul 10 11:58:55 2010: The stack 'CSTACK' is filled to 90% (928 bytes used out of 1024). The warning threshold is set to 90.%
......
FPGA/CPLD
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