RDC-19220/2/4 SERIES
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®
16-BIT MONOLITHIC TRACKING RESOLVER
(LVDT)-TO-DIGITAL CONVERTERS
FEATURES
•
+5 Volt Only Option
•
Only Five External Passive
Components
•
Programmable:
- Resolution: 10-, 12-, 14-, or 16-Bit
- Bandwidth: to 1200 Hz
- Tracking: to 2300 RPS
•
Differential Resolver and LVDT
Input Modes
•
Velocity Output Eliminates
Tachometer
•
Built-In-Test (BIT) Output
•
No 180° Hang-Up
DESCRIPTION
The RDC-19220 Series of converters are low-cost, versatile, 16-bit
monolithic, state-of-the-art Resolver(/LVDT)-to-Digital Converters.
These single-chip converters are available in small 40-pin DDIP, 44-
pin J-Lead, and 44-pin MQFP packages and offer programmable fea-
tures such as resolution, bandwidth and velocity output scaling.
Resolution programming allows selection of 10-, 12-, 14-, or 16-bit,
with accuracies to 2.3 min. This feature combines the high tracking
rate of a 10-bit converter with the precision and low-speed velocity
resolution of a 16-bit converter in one package.
The velocity output (VEL) from the RDC-19220 Series, which can be
used to replace a tachometer, is a 4 V signal (3.5 V with the +5 V only
option) referenced to ground with a linearity of 0.75% of output voltage.
The full scale value of VEL is set by the user with a single resistor.
RDC-19220 Series converters are available with operating tempera-
ture ranges of 0° to +70°C, -40° to +85°C and -55° to +125°C. Military
processing is available.
•
Small Size: Available in DDIP PLCC or
,
MQFP Packages
•
-55° to +125°C Operating
Temperature Available
•
Programmable for LVDT input
APPLICATIONS
With its low cost, small size, high accuracy and versatile performance,
the RDC-19220 Series converter is ideal for use in modern high-per-
formance industrial and military control systems. Typical applications
include motor control, radar antenna positioning, machine tool con-
trol, robotics, and process control. MIL-PRF-38534 processing is
available for military applications.
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7771
©
1999 Data Device Corporation
Data Device Corporation
www.ddc-web.com
+REF -REF
BIT
-VSUM
C
BW
R
1
GAIN
DEMODULATOR
C
BW
10
R
B
VEL
HYSTERESIS
A B
-VCO
R
S
16 BIT
UP/DOWN
COUNTER
E
VCO
&
TIMING
INTEGRATOR
R
V
R
C
A
B
CB
SIN
-S
-
+S
+
COS
CONTROL
TRANSFORMER
-C
-
+C
+
2
+5C
+CAP
-CAP
-5C
-5 V
INVERTER
A GND
+5 V
GND
-5 V
DATA
LATCH
INH
EM BIT 1 EL
THRU
BIT 16
RDC-19220 SERIES
R-12/05-0
FIGURE 1. RDC-19220 SERIES BLOCK DIAGRAM
TABLE 1. RDC-19220 SERIES SPECIFICATIONS
These specifications apply over the rated power supply, temperature
and reference frequency ranges, and 10% signal amplitude variation
and harmonic distortion.
PARAMETER
RESOLUTION
ACCURACY
REPEATABILITY
DIFFERENTIAL LINEARITY
REFERENCE
Type
Voltage:
differential
single ended
overload
Frequency
Input Impedance
SIGNAL INPUT
Type
Voltage: operating
overload
Input impedance
DIGITAL INPUT/OUTPUT
Logic Type
Inputs
UNIT
Bits
Min
LSB
LSB
VALUE
10, 12, 14, or 16
4 or 2 + 1 LSB (note 3)
1 max
1 max in the 16th bit
(+REF, -REF)
Differential
10 max
±5 max
±25 continuous, 100 transient
DC to 40,000 (note 4 & note 9)
10M min // 20 pf
TABLE 1. RDC-19220 SERIES SPECS (CONT’D)
These specifications apply over the rated power supply, temperature
and reference frequency ranges, and 10% signal amplitude variation
and harmonic distortion.
PARAMETER
DYNAMIC
CHARACTERISTICS
Resolution
Tracking Rate (max)(note 4)
Bandwidth(Closed Loop)
(max) (note 4)
Ka (Note 7)
A1
A2
A
B
Acceleration (1 LSB lag)
Settling Time(179° step)
VELOCITY
CHARACTERISTICS
Polarity
Voltage Range(Full Scale)
Scale Factor Error
Scale Factor TC
Reversal Error
Linearity
Zero Offset
Zero Offset TC
Load
Noise
POWER SUPPLIES
Nominal Voltage
Voltage Range
Max Volt. w/o Damage
Current
TEMPERATURE RANGE
Operating (Case)
-30X
-20X
-10X
-A0X
Storage
plastic package
ceramic package
MOISTURE SENSITIVITY
LEVEL MQFP
RDC-19224
THERMAL RESISTANCE
Junction-to-Case (θjc)
40-pin DDIP (ceramic)
44-pin J-Lead (ceramic)
PHYSICAL
CHARACTERISTICS
Size: 40-pin DDIP
44-pin J-Lead
44-pin MQFP
Weight:
40-pin DDIP
44-pin J-Lead
44-pin MQFP
UNIT
VALUE
(at maximum bandwidth)
bits
rps
Hz
1/sec
2
1/sec
1/sec
1/sec
1/sec
deg/s
2
msec
10
1152
1200
5.7M
19.5
295k
2400
1200
2M
2
12
288
1200
5.7M
19.5
295k
2400
1200
500k
8
14
72
600
1.4M
4.9
295k
1200
600
30k
20
16
18
300
360k
1.2
295k
600
300
2k
50
V
P
-
P
V
P
V
Hz
Ohm
(+S, -S, SIN, +C, -C, COS)
Resolver, differential, groundbased
Vrms 2 ±15%
V
±25 continuous
Ohm 10M min//10 pf.
(Note 6)
TTL/CMOS compatible
Logic 0 = 0.8 V max.
Logic 1 = 2.0 V min.
Loading =10 µA max pull-up cur-
rent source to +5 V //5 pF max.
CMOS transient protected
Logic 0 inhibits; Data stable
within 0.3 µs
Logic 0 enables;Data stable with
-in 150 ns (logic 0=Transparent)
Logic 1 = High Impedance
Data High Z within 100 nS
Mode B
resolver 0
"
0
"
1
"
1
LVDT -5 V
"
0
"
1
"
-5 V
A Resolution
0
10 bits
1
12 bits
0
14 bits
1
16 bits
0
8 bits
-5 V
10 bits
-5 V
12 bits
-5 V
14 bits
V
%
PPM/C
%
%
mv
µV/C
kΩ
(Vp/V)%
V
%
V
mA
Positive for increasing angle
±4 (at nominal ps)
10 typ
20 max
100 typ
200 max
0.75 typ
1.3 max
0.25 typ
0.50 max
5 typ
10 max
15 typ
30max
8 min
1 typ
. 125 min 2 max
(note 5)
+5
-5
± 5 ±5
+7
-7
14 typ, 22 max (each)
Inhibit (INH)
Enable Bits 1 to 8 (EM)
Enable Bits 9 to 16 (EL)
Resolution and Mode
Control (A & B)
(see notes 1 and 2.
pre-set to logic 1 note 6)
°C
°C
°C
°C
°C
°C
0 to +70
-40 to +85
-55 to +125
-40 to +125
-65 to +150
-65 to +150
Outputs
Parallel Data (1-16)
JEDEC
2
Converter Busy (CB)
Zero Index
(Zl)
Built-in-Test (BIT)
Drive Capability
10, 12, 14, or 16 parallel lines;
natural binary angle positive
logic (see TABLE 2)
0.25 to 0.75 µs positive pulse
leading edge initiates counter
update.
Logic 1 at all 0s (ENL to -5 V);
LSBs are enabled
Logic 0 for BIT condition.
±100 LSBs of error typ. with a
filter of 500 µS, or total Loss-of-
Signal (LOS)
50 pF +
Logic 0; 1 TTL load, 1.6 mA at
0.4 V max
Logic 1; 10 TTL loads, = 0.4 mA
at 2.8 V min
Logic 0; 100 mV max driving CMOS
Logic 1; +5 V supply minus 100mV
min driving CMOS, High Z;
10 uA//5 pF max
°C/W
°C/W
4.6
2.4
in(mm) 2.0 x 0.6 x 0.2 (50.8 x 15.24 x 5.08)
in(mm) 0.690 square (17.526)
in(mm) 0.394 square (10.0)
Plastic
n/a
n/a
0.017 (0.5)
Ceramic
0.24 (6.80)
0.065 (1.84)
n/a
oz(g)
oz(g)
oz(g)
Data Device Corporation
www.ddc-web.com
3
RDC-19220 SERIES
R-12/05-0
Notes for TABLE 1:(from previous page)
1. Unused data bits are set to logic “0.”
2. In LVDT mode, bit 16 is LSB for 14-bit resolution or bit 12 is LSB for
10-bit resolution.
3. Accuracy spec below for LVDT mode, null to + full scale travel (45
degrees).(2 wire-LVDT configuration).
4 Min part = 0.15% + 1 LSB of full scale “resolution set”.
2 Min part = 0.07% + 1 LSB of full scale “resolution set”
Accuracy spec below for LVDT mode, null to + full scale travel (90
degrees).(3 wire-LVDT configuration).
4 Min part = 0.07% + 1 LSB of full scale “resolution set”.
2 Min part = 0.035% + 1 LSB of full scale “resolution set”
Note that this is the converter spec only and does not consider the
front end external resistor tolerances.
4. See text, General Setup Considerations and HigherTracking Rates.
5. See text: General Setup Considerations for RDC19222.
6. Any unused input pins may be left floating (unconnected). All input
pins are internally pulled-up to +5 Volts.
7. Ka = Acceleration constant, for a full definition see the RD/RDC
application manual acceleration lag section.
8. When using internally generated -5V, the internal -5V charge pump
when measured at the converter pin, can read as low as -20% (or -
4V).
9. No 180° hangup with A/C reference.
φ.
Its output is an analog error angle, or difference angle,
between the two inputs. The CT performs the ratiometric trigono-
metric computation of SINθCOSφ - COSθSINφ = SIN(θ-φ) using
amplifiers, switches, logic and capacitors in precision ratios.
Note:
The transfer function of the CT is normally trigonometric,
but in LDVT mode the transfer function is triangular (linear)
and could thereby convert any linear transducer output.
TABLE 2. DIGITAL ANGLE OUTPUTS
BIT
1(MSB)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DEG/BIT
180
90
45
22.5
11.25
5.625
2.813
1.405
0.7031
0.3516
0.1758
0.0879
0.0439
0.0220
0.0110
0.0055
MIN/BIT
10800
5400
2700
1350
675
337.5
168.75
84.38
42.19
21.09
10.55
5.27
2.64
1.32
0.66
0.33
THEORY OF OPERATION
The RDC-19220 Series of converters are single CMOS custom
monolithic chips. They are implemented using the latest IC tech-
nology which merges precision analog circuitry with digital logic
to form a complete, high-performance tracking Resolver-to-
Digital converter. For user flexibility and convenience, the con-
verter bandwidth, dynamics and velocity scaling are externally
set with passive components.
FIGURE 1 is the functional block diagram of the RDC-19220
Series. The converter operates with ±5 Vdc power supplies.
Analog signals are referenced to analog ground, which is at
ground potential. The converter is made up of two main sections;
a converter and a digital interface. The converter front-end con-
sists of sine and cosine differential input amplifiers. These inputs
are protected to ±25 V with 2 kΩ resistors and diode clamps to
the ±5 Vdc supplies. These amplifiers feed the high accuracy
Control Transformer (CT). Its other input is the 16-bit digital angle
RB C
BW
Note: EM enables the MSBs and EL enables the LSBs.
The converter accuracy is limited by the precision of the com-
puting elements in the CT. For enhanced accuracy, the CT in
these converters uses capacitors in precision ratios, instead of
the more conventional precision resistor ratios. Capacitors, used
as computing elements with op-amps, need to be sampled to
eliminate voltage drifting. Therefore, the circuits are sampled at a
high rate (67 kHz) to eliminate this drifting and at the same time
to cancel out the op-amp offsets.
The error processing is performed using the industry standard
technique for type II tracking R/D converters. The dc error is inte-
grated yielding a velocity voltage which in turn drives a voltage
controlled oscillator (VCO). This VCO is an incremental integra-
tor (constant voltage input to position rate output) which togeth-
VEL
C
BW
/10
RS
-VSUM
R
V
VEL
-VCO
50 pf
C
VCO
CT
RESOLVER
INPUT
(θ)
+
GAIN
DEMOD
R1
VCO
1
C
S
F
S
11 mV/LSB
±1.25 V
THRESHOLD
-
16 BIT
UP/DOWN
COUNTER
H=1
DIGITAL
OUTPUT
(φ)
FIGURE 2. TRANSFER FUNCTION BLOCK DIAGRAM #1
Data Device Corporation
www.ddc-web.com
4
RDC-19220 SERIES
R-12/05-0
er with the velocity integrator forms a type II servo feedback loop.
A lead in the frequency response is introduced to stabilize the
loop and another lag at higher frequency is introduced to reduce
the gain and ripple at the carrier frequency and above. The set-
tings of the various error processor gains and break frequencies
are done with external resistors and capacitors so that the con-
verter loop dynamics can be easily controlled by the user.
GENERAL SETUP CONSIDERATIONS
Note:
For detailed application and technical information see the RD/RDC convert-
er applications manual which is available for download from the DDC web site @
www.ddc-web.com.
DDC has external component selection software which consid-
ers all the criteria below, and in a simple fashion, asks the key
parameters (carrier frequency, resolution, bandwidth, and track-
ing rate) to derive the external component value.
The following recommendations should be considered when
installing the RDC-19220 Series R/D converters:
1) In setting the bandwidth (BW) and Tracking Rate (TR) (select-
ing five external components), the system requirements need
to be considered. For greatest noise immunity, select the min-
imum BW and TR the system will allow.
2) +5 and -5 volt operation:
Power supplies are ±5 V dc. For lowest noise performance it
is recommended that a 0.1 µF or larger cap be connected
from each supply to ground near the converter package.
When using a +5V and -5V supply to power the converter,
RDC-19222 pins 22, 23, 25, 26 must be no connection, and
on RDC-19224 pins 20, 40, 16, 11, must be no connection.
Also, the 10uF cap is not connected to +cap and -cap pins.
3) This converter has 2 internal ground planes, which reduce
noise to the analog input due to digital ground currents. The
resolver inputs and velocity output are referenced to AGND.
The digital outputs and inputs are referenced to GND. The
AGND and GND pins must be tied together as close to the
converter package as possible. Not shorting these pins
together as close to the converter package as possible will
cause unstable converter results.
TRANSFER FUNCTION AND BODE PLOT
The dynamic performance of the converter can be determined from
its Transfer Function Block Diagrams and its Bode Plots (open and
closed loop). These are shown in FIGURES 2, 3, and 4.
The open loop transfer function is as follows:
A
2
S +1
B
Open Loop Transfer Function =
S
2
S +1
10B
(
(
)
)
where A is the gain coefficient and A
2
= A
1
A
2
and B is the frequency of lead compensation.
The components of gain coefficient are error gradient, integrator
gain and VCO gain. These can be broken down as follows:
- Error Gradient = 0.011 volts per LSB (CT + Error Amp + Demod
with 2 Vrms input)
- Integrator Gain = Cs Fs volts per second per volt
1.1 C
BW
- VCO Gain =
1
LSBs per second per volt
1.25 R
V
C
VCO
where: Cs = 10 pF
Fs = 67 kHz when Rs = 30 kΩ
Fs = 100 kHz when Rs = 20 kΩ
Fs = 134 kHz when Rs = 15 kΩ
C
VCO
= 50 pF
R
V
, R
B
, and C
BW
are selected by the user to set velocity scaling
and bandwidth.
-1
2d
GAIN = 4
c
b/o
t
(CRITICALLY DAMPED)
ERROR PROCESSOR
RESOLVER
INPUT
(θ)
+
-
CT
e
A1 S + 1
B
S
S +1
10B
VELOCITY
OUT
VCO
A
2
S
DIGITAL
POSITION
OUT (φ)
2A
OPEN LOOP
B
A
-6
db
/oc
ω
(rad/sec)
10B
t
(B = A/2)
GAIN = 0.4
f
BW
= BW (Hz) =
2A
π
H=1
CLOSED LOOP
2A
2 2A
ω
(rad/sec)
FIGURE 3. TRANSFER FUNCTION
BLOCK DIAGRAM #2
Data Device Corporation
www.ddc-web.com
5
FIGURE 4. BODE PLOTS
RDC-19220 SERIES
R-12/05-0
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