Supertex inc.
High Speed Quad MOSFET Driver
Features
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6ns rise and fall time
2A peak output source/sink current
1.2V to 5V input CMOS compatible
±5V to ±12V supply voltage operation
Smart Logic threshold
Low jitter design
Quad matched channels
Drives two N and two P-channel MOSFETs
Outputs can swing below ground
Built-in level translator for negative gate bias
User-defined damping for return-to-zero applications
Non-inverting gate driver OUT
D
for easy logic
Low inductance quad flat no-lead package
Thermally-enhanced package
MD1813
Initial Release
General Description
The Supertex MD1813 is a high-speed quad MOSFET driver. It is
designed to drive two N and two P-channel, high voltage, DMOS FETs for
medical ultrasound applications, but may be used in any application that
needs a high output current for a capacitive load. The input stage of the
MD1813 is a high-speed level translator that is able to operate from logic
input signals of 1.2 to 5.0 volt amplitude. An adaptive threshold circuit is
used to set the level translator threshold to the average of the input logic
0 and logic 1 levels. The level translator uses a proprietary circuit, which
provides DC coupling together with high-speed operation.
The output stage of the MD1813 has separate power connections,
enabling the output signal L and H levels to be chosen independently
from the driver supply voltages. As an example, the input logic levels may
be 0V and 1.8V, the control logic may be powered by +5V and –5V, and
the output L and H levels may be varied anywhere over the range of –5V
to +5V. The output stage is capable of peak currents of up to ±2 amps,
depending on the supply voltages used and load capacitance. The OE
pin serves a dual purpose. First, its logic H level is used to compute the
threshold voltage level for the channel input level translators. Secondly,
when OE is low, the outputs are disabled, with the A output high and the
B output low. This assists in properly pre-charging the coupling capacitors
that may be used in series in the gate drive circuit of an external PMOS
and NMOS. A built-in level shifter is for PMOS gate negative bias driving.
It enables the user-defined damping control to generate return-to-zero
bipolar output pulses. The MD1813 has a non-inverting driver OUT
D
for
easy logic.
Applications
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Ultrasound PN code transmitter
Medical ultrasound imaging
Piezoelectric transducer drivers
Nondestructive evaluation
High speed level translator
High voltage bipolar pulser
Typical Application Circuit
+100V
+10V
0.22 F
14
V
DD
11
V
H
OUT
A
13
OUT
B
12
OUT
G
10
2K
OUT
C
DAMP
IN
D
6
GND
3
V
SS
7
2
V
L
V
NEG
4
-10V
10nF
OUT
D
8
9
10nF
-100V
+10V
1 F
0.47 F
10nF
ENAB
16 OE
15 IN
A
3.3V CMOS
Logic Inputs
PULSE
1
IN
B
LT
5 IN
C
Supertex
TC6320
1 F
To Piezoelectric
Transducer
0.47 F
Supertex
MD1813
Supertex
TC2320
NR031706
Supertex inc.
·
1235 Bordeaux Drive, Sunnyvale, CA 94089
·
Tel: (408) 222-8888
·
FAX: (408) 222-4895
·
www.supertex.com
1
MD1813
Package Option
Device
16-lead 4x4x0.9 QFN
MD1813
-G indicates package is RoHS compliant (‘Green’)
MD1813K6-G
16-Lead QFN (K6) Package
16-Lead QFN (K6) Pin Configuration
16
13
1
12
MD1813
4
9
5
8
Top View
Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Function
IN
B
V
L
GND
V
NEG
IN
C
IN
D
V
SS
OUT
D
OUT
C
OUT
G
V
H
OUT
B
OUT
A
V
DD
IN
A
OE
Description
Logic input. Controls OUT
B
when OE is high.
.
Supply voltage for N-channel output stage.
Device ground.
Supply voltage the auxiliary gate drive.
Logic input. Controls OUT
C
when OE is high.
Logic input. Controls OUT
D
when OE is high.
Supply voltage for low-side analog, level shifter, and gate drive circuit.
Output driver.
Output driver.
Auxiliary output driver.
Supply voltage for P-channel output stage
Output driver.
Output driver.
Supply voltage for high-side analog, level shifter, and gate drive circuit.
Logic input. Controls OUT
A
when OE is high.
Output enable logic input.
Note: Thermal pad and pin #4, V
NEG
must be connected externally.
NR031706
2
MD1813
Absolute Maximum Ratings
Parameter
V
DD
-V
SS
, Logic Supply Voltage
V
H
, Output High Supply Voltage
V
L
, Output Low Supply Voltage
Vss, Low Side Supply Voltage
V
NEG
-V
SS
, Negative Supply Voltage
Logic Input Levels
Maximum Junction Temperature
Storage Temperature
Soldering Temperature
Package Power Dissipation
Value
-0.5V to +13.5V
V
L
-0.5V to V
DD
+0.5V
V
SS
-0.5V to V
H
+0.5V
-7V to +0.5V
V
SS
-13.5V to V
SS
+0.5V
V
SS
-0.5V to V
SS
+7V
+125°C
-65°C to 150°C
235°C
2.2W
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to device ground.
DC Electrical Characteristics
(V
H
= V
DD
= 12V, V
L
= V
SS
= GND = 0V, V
NEG
= -12V, V
OE
= 3.3V, T
J
= 25
O
C)
Symbol
V
DD
-V
SS
V
SS
V
H
V
L
V
NEG
I
DDQ
I
HQ
I
NEGQ
I
DD
I
H
I
NEG
V
IH
V
IL
I
IH
I
IL
V
IH
V
IL
R
IN
C
IN
Parameter
Logic supply voltage
Low side supply voltage
Output high supply voltage
Output low supply voltage
Negative supply voltage
V
DD
quiescent current
V
H
quiescent current
V
NEG
quiescent current
V
DD
average current
V
H
average current
V
NEG
average current
Input logic voltage high
Input logic voltage low
Input logic current high
Input logic current low
OE Input logic voltage high
OE Input logic voltage low
Input logic impedance to GND
Logic input capacitance
Min
4.5
-5.5
V
SS
+2
V
SS
-13
-
-
Typ
-
-
-
-
-
0.9
-
120
Max
13
0
V
DD
V
DD
-2
V
SS
-2
-
10
-
-
-
-
5.0
0.3
1.0
1.0
5.0
0.3
30
10
Units
V
V
V
V
V
mA
µA
µA
mA
mA
mA
V
V
µA
µA
V
V
KΩ
pF
Conditions
---
---
---
---
May connect to V
SS
if OUT
G
not used
---
-
-
-
V
OE
-0.3
0
-
-
1.8
0
12
-
8.0
22
1.0
-
-
-
-
-
-
20
5.0
V
H
= V
DD
= 12V, V
SS
= V
LL
= GND = 0V,
V
NEG
= -12V,
One channel on at 5.0Mhz, No load
For logic inputs IN
A
, IN
B
, IN
C
, and IN
D
For logic input OE
---
NR031706
3
MD1813
Outputs
(V
H
= V
DD
= 12V, V
L
= V
SS
= GND = 0V, V
NEG
= -12V, V
OE
= 3.3V, T
J
= 25
O
C)
Symbol
R
SINK
R
SOURCE
I
SINK
I
SOURCE
Parameter
Output sink resistance
Output source resistance
Peak output sink current
Peak output source current
Min
-
-
-
-
Typ
-
-
2.0
2.0
Max
12.5
12.5
-
-
Units
Ω
Ω
A
A
Conditions
I
SINK
= 50mA
I
SOURCE
= 50mA
---
---
AC Electrical Characteristics
(V
H
= V
DD
= 12V, V
L
= V
SS
= GND = 0V, V
NEG
= -12V, V
OE
= 3.3V, T
J
= 25
O
C)
Symbol
t
irf
t
PLH
t
PHL
t
POE
t
PCG
t
r
t
f
l t
r
- t
f
l
l t
PLH
-t
PHL
l
∆t
dm
Parameter
Input or OE rise & fall time
Propagation delay when output is
from low to high
Propagation delay when output is
from high to low
Propagation delay OE to output
Propagation delay IN
C
to OUT
G
Output rise time
Output fall time
Rise and fall time matching
Propagation low to high and high
to low matching
Propagation delay matching
Min
-
-
-
-
-
-
-
-
-
-
Typ
-
7.0
7.0
9.0
28
6.0
6.0
1.0
1.0
±2.0
Max
10
-
-
-
-
-
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
Logic input edge speed requirement
C
LOAD
= 1000pF, see timing diagram
Input signal rise/fall time 2ns
for each channel
Device to device delay match
Logic Truth Table
Logic Inputs
OE
H
H
H
H
L
OE*
IN
A
L
L
H
H
X
IN
C
L
L
H
H
IN
B
L
H
L
H
X
IN
D
L
H
L
H
OUT
C
V
H
V
H
V
L
V
L
OUT
A
V
H
V
H
V
L
V
L
V
H
OUT
G
V
SS
V
SS
V
NEG
V
NEG
Output
OUT
B
V
H
V
L
V
H
V
L
V
L
OUT
D
**
V
L
V
H
V
L
V
H
Note:
* No control to OUT
G
, OUT
C
, or OUT
D
,
** OUT
D
is non-inverting output
NR031706
4
MD1813
Application Information
For proper operation of the MD1813, low inductance bypass
capacitors should be used on the various supply pins. The GND
pin should be connected to the logic ground. The IN
A
, IN
B
, IN
C
, IN
D
and OE pins should be connected to a logic source with a swing
of GND to V
CC
, where V
CC
is 1.2 to 5.0 volts. Good trace practices
should be followed corresponding to the desired operating speed.
The internal circuitry of the MD1813 is capable of operating up
to 100MHz, with the primary speed limitation being the loading
effects of the load capacitance. Because of this speed and the
high transient currents that result with capacitive loads, the bypass
capacitors should be as close to the chip pins as possible. Unless
the load specifically requires bipolar drive, the V
SS
, and V
L
pins
should have low inductance feed-through connections directly to a
ground plane. If these voltages are not zero, then they need bypass
capacitors in a manner similar to the positive power supplies. The
power connections V
DD
should have a ceramic bypass capacitor to
the ground plane with short leads and decoupling components to
prevent resonance in the power leads.
Output drivers, OUT
A
and OUT
C
, drive the gate of an external P-
channel MOSFET, while output drivers OUT
B
and OUT
D
drive the
gate of an external N-channel MOSFET, and they all swing from
V
H
to V
L
. The auxiliary output drive, OUT
G
, swings from V
SS
to V
NEG
,
and drives the external P-channel MOSFET as negative bias via a
2KΩ series resistor.
The voltages of V
H
and V
L
decide the output signal levels. These
two pins can draw fast transient currents of up to 2A, so they
should be provided with an appropriate bypass capacitor located
next to the chip pins. A ceramic capacitor of up to 1.0µF may be
appropriate, with a series ferrite bead to prevent resonance in the
power supply lead coming to the capacitor. Pay particular attention
to minimizing trace lengths, current loop area, and using sufficient
trace width to reduce inductance. Surface mount components are
highly recommended. Since the output impedance of this driver is
very low, in some cases it may be desirable to add a small series
resistance in series with the output signal to obtain better waveform
transitions at the load terminals. This will of course reduce the
output voltage slew rate at the terminals of a capacitive load.
The OE pin sets the threshold level of logic for inputs (V
OE
+ V
GND
) /
2. When OE is low, OUT
A
is at V
H
. OUT
B
is at V
L
, regardless of the
inputs IN
A
or IN
B
. This pin will not control OUT
C
, OUT
D
, or OUT
G
.
Pay particular attention that parasitic couplings are minimized from
the output to the input signal terminals. The parasitic feedback may
cause oscillations or spurious waveform shapes on the edges of
signal transitions. Since the input operates with signals down to
1.2V, even small coupled voltages may cause problems. Use of
a solid ground plane and good power and signal layout practices
will prevent this problem. Be careful that a circulating ground
return current from a capacitive load cannot react with common
inductance to cause noise voltages in the input logic circuitry. Best
timing performance is obtained for OUT
C
when the voltage of (V
SS
-
V
NEG
) = (V
H
-V
L
).
When input logic is high, output will swing to V
L
, and when input
logic is low, output will swing to V
H
. All inputs must be kept low until
the device is powered up.
NR031706
5
FPGA/CPLD
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