Si501/2/3
32
K
H
Z
–100
MH
Z
CMEMS
O
SC ILLA TOR
Features
Wide frequency range: 32 kHz to
100 MHz
Contact Silicon Labs for
frequencies above 100 MHz
Si501 single frequency w/ OE
Si502 dual frequency w/ OE/FS
Si503 quad frequency w/ FS
±20/30/50 ppm frequency stability
including 10-year aging
LVCMOS output
Low period jitter
Low power
Continuous supply voltage range:
+1.71 V to +3.63 V
User selectable tRise/tFall options
Glitchless start and stop
Excellent short-term stability, long-
term aging
Industry standard footprints:
2x2.5, 2.5x3.2, 3.2x5 mm
RoHS compliant, Pb-free
Short lead times: <2 weeks
–20 to +70 °C: Extnd commercial
–40 to +85 °C: Industrial
The Si50x family also includes the
Si504 for in-circuit programmability
(See the Si504 Data Sheet)
Applications
Storage (SATA/SAS/PCIe)
General purpose processors
Industrial controllers
Embedded controllers
Motor control
Flow control
Office/Home automation
IP cameras/surveillance
Display and control panels
Outdoor electronics
Multi-function printers
Office equipment
Description
The Si501/2/3 CMEMS oscillator family provides monolithic, MEMS-based IC
replacements for traditional crystal oscillators. Silicon Laboratories’ CMEMS
technology combines standard CMOS + MEMS in a single, monolithic IC to provide
integrated, high-quality and high-reliability oscillators. Each device is factory tested
and configured for guaranteed performance to data sheet specifications across
voltage, process, temperature, shock, vibration, and aging.
Additional information on the Si50x CMEMS oscillator architecture and CMEMS
technology is available in white papers on the Silicon Labs website at
www.siliconlabs.com/cmems.
Ordering Information:
See Section 5.
Pin Assignments
FS/OE 1
GND 2
Patents pending
4 V
DD
3 CLK
Functional Block Diagram
VDD
LDO
Digital
Frequency-Locked
Loop (FLL)
Resonator
& Oscillator
Temperature
Sensor
VCO
FS/OE
Temp Comp /
Digital
Control
NVM RAM ROM
M
M
÷
CLK
GND
Rev. 1.0 6/14
Copyright © 2014 by Silicon Laboratories
Si501/2/3
Si501/2/3
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Si501/2/3 Typical Applications Circuits, AC Waveforms, and Functional
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1. Si501/2 Applications Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.2. Si501/2 AC Waveforms and Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . .9
2.3. Si503 Applications Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4. Si503 AC Waveform and Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1. OE Enable and Disable States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2. Output Rise and Fall settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1. Si501 Ordering Guide and Part Number Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5.2. Si502 Ordering Guide and Part Number Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5.3. Si503 Ordering Guide and Part Number Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
6. Package Dimensions and Land Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1. Package Outline: 3.2 x 5 mm 4-pin DFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2. Package Outline: 2.5 x 3.2 mm 4-pin DFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3. Package Outline: 2 x 2.5 mm 4-pin DFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
7.1. 3.2 x 5 mm Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.2. 3.2 x 5 mm Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.3. 2.5 x 3.2 mm Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.4. 2.5 x 3.2 mm Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
7.5. 2 x 2.5 mm Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.6. 2 x 2.5 mm Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2
Rev. 1.0
Si501/2/3
1. Electrical Specifications
Table 1. Recommended Operating Conditions
V
DD
=1.71 to 3.63 V, T
A
= –40 to 85
C, unless otherwise specified
Parameter
Supply Voltage
1
Supply Current
Symbol
V
DD
I
DD1
Test Condition
Min
1.71
Typ
—
1.7
5.3
3.9
7.6
1.7
3.9
670
0.3
—
—
50
—
—
Max
3.63
2.5
6.5
4.9
8.9
2.5
4.9
890
1
—
0.30 x
V
DD
60
70
85
Unit
V
mA
mA
mA
mA
mA
mA
µA
µA
V
V
kΩ
C
C
C
L
=4 pF, 3.3 V
DD
, F
CLK
=1.0 MHz, low
power option
C
L
=4 pF, 3.3 V
DD
, F
CLK
=100 MHz, low
power option
C
L
=4 pF, 3.3 V
DD
, F
CLK
=1.0 MHz, low
jitter option
C
L
=4 pF, 3.3 V
DD
, F
CLK
=100 MHz, low
jitter option
—
—
—
—
—
—
—
—
0.70 x
V
DD
—
40
–20
–40
Static Supply
Current
I
DD2
Mode=Stop
2
, low power option
F
CLK
=1 MHz
Mode=Stop
2
, low jitter option
F
CLK
=1 MHz
Mode=Doze
2
Mode=Sleep
2
Input High Voltage
Input Low Voltage
OE Internal Pull
Resistor
Operating
Temperature
V
IH
V
IL
R
I
T
A
FS/OE pin
FS/OE pin
Ordering option
Extended commercial grade
Industrial grade
Notes:
1.
The supply voltage range is continuous from 1.71 to 3.63 V.
2.
Si501 and Si502 only. Si503 has FS only and does not support Stop, Doze, or Sleep. See Section 3. Functional
Description for more information on operational modes.
Rev. 1.0
3
Si501/2/3
Table 2. Output Clock Characteristics
V
DD
=1.71 to 3.63 V, T
A
= –40 to 85
C, unless otherwise specified.
Parameter
Frequency
Range
Clock Period
Total Stability
1
Symbol
F
CLK
T
CLK
F
STAB
1/F
CLK
Test Condition
Min
0.032
31,250
–20
–30
–50
Typ
—
—
—
—
—
±2
2.5
2.5
1.7
—
—
—
—
Max
100
10
+20
+30
+50
—
4
5
2.55
1.5 x T
CLK
+
35
225
1.5 x T
CLK
+
35
5
Unit
MHz
ns
ppm
ppm
ppm
ppm
ms
ms
ms
ns
µs
ns
ms
Initial
Accuracy
Startup Time
2
Resume
Time
3,4
F
I
T
SU
T
RUN
Measured at 25
C at the time of
shipping
From V
DD
crossing 1.71 V to first
clock output
From Sleep mode
From Doze mode
From Stop mode
5
—
—
—
—
—
—
—
—
Output Disable
Time
3,4
T
D
To Sleep/Doze mode, from output
running
To Stop, from output running
Frequency
Update
Time
4,6
T
NEW_FREQ
Notes:
1.
Orderable option. Stability budget consists of initial tolerance, operating temperature range, rated power supply voltage
change, load change, 10-year aging, shock, and vibration.
2.
Hold FS/OE high (strong or weak) during powerup for fastest time to clock.
3.
Si501 and Si502 only. Si503 has FS only and does not support Stop, Doze, or Sleep.
4.
Asserted FS/OE actions must be held stable for the maximum duration of the invoked FS/OE event (e.g., T
RUN
,
T
NEW_FREQ
, T
D
, etc).
5.
If the Si502 frequency is switched while the device is in Stop mode, the frequency prior to Stop will be output briefly until
the glitchless switch to the other frequency. Doze mode and Sleep mode do not have this behavior.
6.
Si502 and Si503 only. Si501 is a single frequency device with OE only.
4
Rev. 1.0
Si501/2/3
Table 3. Output Clock Levels and Symmetry
V
DD
= 1.71 to 3.63 V, T
A
= –40 to 85
C unless otherwise indicated.
Parameter
Output High Voltage
Output Low Voltage
Rise/Fall
Time
1
Symbol
V
OH
V
OL
tRise
/tFall
Test Condition
1st ordering option code: A and H
I
OH
=–4 mA
1st ordering option code: A and H
I
OH
=+4 mA
1
st
ordering option code
2
: A and H
Z
0
=25
@ 3.3 V
1
st
ordering option code: B and J
Z
0
= 50
@
3.3 V
1
st
ordering option code: C and K
Z
0
= 50
@
2.5 V
1
st
ordering option code: D and L
Z
0
= 50
@
1.8 V
1
st
ordering option code: E and M
Z
0
= 110
@
3.3 V
1
st
ordering option code: F and N
Z
0
=220
@ 3.3 V
3
1
st
ordering option code: G and P
Z
0
=440
@ 3.3 V
3
Min
0.90 x
V
DD
—
0.4
1
1
1
2
4
7
45
Typ
—
—
0.7
2
1.3
1.3
1.3
3
5
8
50
Max
—
0.10 x
V
DD
1.2
1.6
1.6
1.6
4
7
11
55
Unit
V
V
ns
ns
ns
ns
ns
ns
ns
%
Duty Cycle
DC
Drive strength selected such that
tRise/tFall (20% to 80%)<10% of
period
Notes:
1.
C
L
=15 pF, tRise/tFall (20% to 80%), 3.3 V, unless otherwise stated.
2.
Recommended series termination resistor (R
S
) = 24.9
for Z
0
=50
3.
Ordering options F, N, G, and P are not recommended for F
CLK
> 5 MH
2
.
Rev. 1.0
5
FPGA/CPLD
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